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Re: [PATCH-for-5.2?] target/mips/translate: Check R6 reserved encoding f
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [PATCH-for-5.2?] target/mips/translate: Check R6 reserved encoding for Load Linked Word |
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Date: |
Tue, 24 Nov 2020 17:15:30 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 |
On 11/24/20 4:59 PM, Richard Henderson wrote:
> On 11/24/20 5:45 AM, Philippe Mathieu-Daudé wrote:
>> Release 6 recoded the 'Load Linked Word' using SPECIAL3 opcode,
>> this opcode (0b110000) is now reserved.
>>
>> Ref: A.2 Instruction Bit Encoding Tables:
>>
>> "6Rm instructions signal a Reserved Instruction exception
>> when executed by a Release 6 implementation."
>>
>> The check was added in commit 4368b29a26e ("target-mips: move
>> LL and SC instructions") but got lost during latter refactor
>> in commit d9224450208 ("target-mips: Tighten ISA level checks").
>
> I think git blame is confused here -- d9224450208 isn't the one that broke
> things. The patch has:
>
>
> + case OPC_LL: /* Load and stores */
> + check_insn(ctx, ISA_MIPS2);
> + /* Fallthrough */
> + case OPC_LWL:
> case OPC_LWR:
> - case OPC_LL:
> check_insn_opc_removed(ctx, ISA_MIPS32R6);
> + /* Fallthrough */
Sorry I have been confused by the /* Fallthrough */ ...
The check is below.
Self-NAck then.