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[PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_in
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init() |
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Date: |
Tue, 8 Dec 2020 01:36:52 +0100 |
Extract the logic initialization of the MSA registers from
the generic initialization.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 3 +++
target/mips/translate.c | 33 +++++++++++++++++++--------------
2 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index dbf7df7ba6d..765018beeea 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -80,4 +80,7 @@ extern TCGv bcond;
} \
} while (0)
+/* MSA */
+void msa_translate_init(void);
+
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 95d07e837c0..bbe06240510 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31551,6 +31551,24 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, int
flags)
}
}
+static void msa_translate_init(void)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
+ /*
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
+ */
+ msa_wr_d[i * 2] = fpu_f64[i];
+ off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
+ msa_wr_d[i * 2 + 1] =
+ tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
+ }
+}
+
void mips_tcg_init(void)
{
int i;
@@ -31566,20 +31584,7 @@ void mips_tcg_init(void)
fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
}
- /* MSA */
- for (i = 0; i < 32; i++) {
- int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
-
- /*
- * The MSA vector registers are mapped on the
- * scalar floating-point unit (FPU) registers.
- */
- msa_wr_d[i * 2] = fpu_f64[i];
- off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
- msa_wr_d[i * 2 + 1] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
- }
-
+ msa_translate_init();
cpu_PC = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.PC), "PC");
for (i = 0; i < MIPS_DSP_ACC; i++) {
--
2.26.2
- [PATCH 00/17] target/mips: Convert MSA ASE to decodetree, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 01/17] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 02/17] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 04/17] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init(),
Philippe Mathieu-Daudé <=
- [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 12/17] target/mips: Extract MSA helpers from op_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 14/17] target/mips: Declare gen_msa/_branch() in 'translate.h', Philippe Mathieu-Daudé, 2020/12/07