Re: [PATCH v2 0/3] target/nios2: Roll cpu_pic/nios2_iic code into CPU itself

[Peter Maydell]

On Sun, 29 Nov 2020 at 17:40, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The Nios2 architecture supports two different interrupt controller
> options:
>
>  * The IIC (Internal Interrupt Controller) is part of the CPU itself;
>    it has 32 IRQ input lines and no NMI support.  Interrupt status is
>    queried and controlled via the CPU's ipending and istatus
>    registers.
>
>  * The EIC (External Interrupt Controller) interface allows the CPU
>    to connect to an external interrupt controller.  The interface
>    allows the interrupt controller to present a packet of information
>    containing:
>     - handler address
>     - interrupt level
>     - register set
>     - NMI mode
>
> QEMU does not model an EIC currently.  We do model the IIC, but its
> implementation is split across code in hw/nios2/cpu_pic.c and
> hw/intc/nios2_iic.c.  The code in those two files has no state of its
> own -- the IIC state is in the Nios2CPU state struct.
>
> Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they
> can have GPIO input lines themselves, so we can implement the IIC
> directly in the CPU object the same way that real hardware does.
>
> This fixes a Coverity-reported trivial memory leak of the IRQ array
> allocated in nios2_cpu_pic_init().  I think the diffstat on the
> overall patchset is also a pretty good argument for the refactor :-)

Now the tree is open for 6.0 development I'll take this series
via target-arm.next.

thanks
-- PMM