[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v12 22/23] cpu: move cc->transaction_failed to tcg_ops
From: |
Claudio Fontana |
Subject: |
[PATCH v12 22/23] cpu: move cc->transaction_failed to tcg_ops |
Date: |
Sat, 12 Dec 2020 16:55:29 +0100 |
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/cpu.h | 18 ++++++++----------
hw/mips/jazz.c | 9 +++++++--
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 4 ++--
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 4 +++-
target/riscv/cpu.c | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/sparc/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/xtensa/helper.c | 4 ++--
include/hw/core/tcg-cpu-ops.h.inc | 13 +++++++++++++
13 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index e7eb0397e4..30e4854305 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -89,8 +89,6 @@ struct TranslationBlock;
* @has_work: Callback for checking if there is work to do.
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
- * @do_transaction_failed: Callback for handling failed memory transactions
- * (ie bus faults or external aborts; not MMU faults)
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian. Non-configurable
* CPUs can use the default implementation of this method. This method should
@@ -159,10 +157,6 @@ struct CPUClass {
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
- void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
- unsigned size, MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
@@ -849,6 +843,7 @@ static inline void cpu_unaligned_access(CPUState *cpu,
vaddr addr,
cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
}
+#ifdef CONFIG_TCG
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -858,12 +853,15 @@ static inline void cpu_transaction_failed(CPUState *cpu,
hwaddr physaddr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed)
{
- cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
- mmu_idx, attrs, response, retaddr);
+ if (!cpu->ignore_memory_transaction_failures &&
+ cc->tcg_ops.do_transaction_failed) {
+ cc->tcg_ops.do_transaction_failed(cpu, physaddr, addr, size,
+ access_type, mmu_idx, attrs,
+ response, retaddr);
}
}
-#endif
+#endif /* CONFIG_TCG */
+#endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index f9442731dd..46c71a0ac8 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -116,6 +116,8 @@ static const MemoryRegionOps dma_dummy_ops = {
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE
\
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
+
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -137,6 +139,7 @@ static void mips_jazz_do_transaction_failed(CPUState *cs,
hwaddr physaddr,
(*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
mmu_idx, attrs, response, retaddr);
}
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
@@ -205,8 +208,10 @@ static void mips_jazz_init(MachineState *machine,
* memory region that catches all memory accesses, as we do on Malta.
*/
cc = CPU_GET_CLASS(cpu);
- real_do_transaction_failed = cc->do_transaction_failed;
- cc->do_transaction_failed = mips_jazz_do_transaction_failed;
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
+ real_do_transaction_failed = cc->tcg_ops.do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = mips_jazz_do_transaction_failed;
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
/* allocate RAM */
memory_region_add_subregion(address_space, 0, machine->ram);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 66f1166672..a1696bebeb 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -225,7 +225,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void
*data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = alpha_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = alpha_cpu_do_transaction_failed;
cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ed552a7bb5..525f9311dc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2271,11 +2271,11 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY)
- cc->do_transaction_failed = arm_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
-#endif
+#endif /* CONFIG_TCG */
}
#ifdef CONFIG_KVM
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 3e84de772c..3f60c99865 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -285,7 +285,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill;
#if defined(CONFIG_SOFTMMU)
- cc->do_transaction_failed = m68k_cpu_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = m68k_cpu_transaction_failed;
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 4f95248b2e..fa57a324dc 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -327,7 +327,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = mb_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mb_cpu_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = mb_cpu_transaction_failed;
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 25c4a55a6a..fe8bca41b7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -241,7 +241,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = mips_cpu_do_transaction_failed;
cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
@@ -253,6 +252,9 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt;
cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
+ cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
+#endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */
cc->gdb_num_core_regs = 73;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a815569cc..7dfd8d7339 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -555,7 +555,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = riscv_cpu_do_transaction_failed;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a2787b1d48..4c3e0382ce 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -667,7 +667,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
env->badaddr = addr;
riscv_raise_exception(env, cs->exception_index, retaddr);
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 3f23aa5962..009d0f07c3 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -873,7 +873,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void
*data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY
- cc->do_transaction_failed = sparc_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 3ff025f0fe..fc52fde696 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -205,7 +205,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void
*data)
#ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
- cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
+ cc->tcg_ops.do_transaction_failed = xtensa_cpu_do_transaction_failed;
#endif
cc->tcg_ops.debug_excp_handler = xtensa_breakpoint_handler;
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 05e2b7f70a..eeffee297d 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -261,7 +261,7 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
cpu_loop_exit_restore(cs, retaddr);
}
-#else
+#else /* !CONFIG_USER_ONLY */
void xtensa_cpu_do_unaligned_access(CPUState *cs,
vaddr addr, MMUAccessType access_type,
@@ -337,4 +337,4 @@ void xtensa_runstall(CPUXtensaState *env, bool runstall)
qemu_cpu_kick(cpu);
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
diff --git a/include/hw/core/tcg-cpu-ops.h.inc
b/include/hw/core/tcg-cpu-ops.h.inc
index 89fd3d97b5..5d46693678 100644
--- a/include/hw/core/tcg-cpu-ops.h.inc
+++ b/include/hw/core/tcg-cpu-ops.h.inc
@@ -53,6 +53,19 @@ typedef struct TcgCpuOperations {
bool probe, uintptr_t retaddr);
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
+
+#ifndef CONFIG_USER_ONLY
+ /**
+ * @do_transaction_failed: Callback for handling failed memory transactions
+ * (ie bus faults or external aborts; not MMU faults)
+ */
+ void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
+ unsigned size, MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+
+#endif /* !CONFIG_USER_ONLY */
+
} TcgCpuOperations;
#endif /* TCG_CPU_OPS_H */
--
2.26.2
- Re: [PATCH v12 16/23] cpu: Move synchronize_from_tb() to tcg_ops, (continued)
[PATCH v12 20/23] target/arm: do not use cc->do_interrupt for KVM directly, Claudio Fontana, 2020/12/12
[PATCH v12 19/23] cpu: Move debug_excp_handler to tcg_ops, Claudio Fontana, 2020/12/12
[PATCH v12 09/23] tcg: cpu_exec_{enter,exit} helpers, Claudio Fontana, 2020/12/12
[PATCH v12 10/23] tcg: make CPUClass.cpu_exec_* optional, Claudio Fontana, 2020/12/12
[PATCH v12 08/23] i386: tcg: remove inline from cpu_load_eflags, Claudio Fontana, 2020/12/12
[PATCH v12 03/23] i386: move hax accel files into hax/, Claudio Fontana, 2020/12/12
[PATCH v12 22/23] cpu: move cc->transaction_failed to tcg_ops,
Claudio Fontana <=
[PATCH v12 18/23] cpu: Move tlb_fill to tcg_ops, Claudio Fontana, 2020/12/12
[PATCH v12 23/23] cpu: move do_unaligned_access to tcg_ops, Claudio Fontana, 2020/12/12
[PATCH v12 13/23] cpu: Introduce TCGCpuOperations struct, Claudio Fontana, 2020/12/12
[PATCH v12 12/23] cpu: Remove unnecessary noop methods, Claudio Fontana, 2020/12/12
[PATCH v12 02/23] i386: move whpx accel files into whpx/, Claudio Fontana, 2020/12/12
[PATCH v12 21/23] cpu: move cc->do_interrupt to tcg_ops, Claudio Fontana, 2020/12/12
[PATCH v12 07/23] i386: move TCG cpu class initialization to tcg/, Claudio Fontana, 2020/12/12
Re: [PATCH v12 00/23] i386 cleanup PART 1, no-reply, 2020/12/12
Re: [PATCH v12 00/23] i386 cleanup PART 1, Eduardo Habkost, 2020/12/14