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[PATCH v3 03/15] riscv: spike: Remove target macro conditionals
From: |
Alistair Francis |
Subject: |
[PATCH v3 03/15] riscv: spike: Remove target macro conditionals |
Date: |
Mon, 14 Dec 2020 12:34:04 -0800 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
include/hw/riscv/spike.h | 6 ------
hw/riscv/spike.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index cddeca2e77..cdd1a13011 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -47,10 +47,4 @@ enum {
SPIKE_DRAM
};
-#if defined(TARGET_RISCV32)
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
-#endif
-
#endif
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index facac6e7d2..29f07f47b1 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -317,7 +317,7 @@ static void spike_machine_class_init(ObjectClass *oc, void
*data)
mc->init = spike_board_init;
mc->max_cpus = SPIKE_CPUS_MAX;
mc->is_default = true;
- mc->default_cpu_type = SPIKE_V1_10_0_CPU;
+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
--
2.29.2
- [PATCH v3 00/15] RISC-V: Start to remove xlen preprocess, Alistair Francis, 2020/12/14
- [PATCH v3 01/15] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/14
- [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/14
- [PATCH v3 03/15] riscv: spike: Remove target macro conditionals,
Alistair Francis <=
- [PATCH v3 04/15] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/14
- [PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 06/15] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 07/15] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 08/15] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/14
- [PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/14