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[RFC v2 04/15] target/riscv: rvb: logic-with-negate
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From: |
frank . chang |
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Subject: |
[RFC v2 04/15] target/riscv: rvb: logic-with-negate |
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Date: |
Wed, 16 Dec 2020 10:01:29 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 18 ++++++++++++++++++
target/riscv/translate.c | 21 +++++++++++++++++++++
3 files changed, 43 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ac4d8395a45..85421dccb99 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,3 +598,7 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
pcnt 011000 000010 ..... 001 ..... 0010011 @r2
+
+andn 0100000 .......... 111 ..... 0110011 @r
+orn 0100000 .......... 110 ..... 0110011 @r
+xnor 0100000 .......... 100 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index f5930f2ad53..6016ceefd64 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -35,6 +35,24 @@ static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a)
return gen_unary(ctx, a, &tcg_gen_ctpop_tl);
}
+static bool trans_andn(DisasContext *ctx, arg_andn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_andn);
+}
+
+static bool trans_orn(DisasContext *ctx, arg_orn *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_orn);
+}
+
+static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, &gen_xnor);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 4c9eb86e630..fb0b2fd0728 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -711,6 +711,27 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
#endif
+static void gen_andn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_andc_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
+static void gen_orn(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_orc_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
+static void gen_xnor(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_eqv_tl(ret, arg1, arg2);
+ tcg_temp_free(t);
+}
+
#ifdef TARGET_RISCV64
static void gen_ctzw(TCGv ret, TCGv arg1)
--
2.17.1
- [RFC v2 00/15] support subsets of bitmanip extension, frank . chang, 2020/12/15
- [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2020/12/15
- [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2020/12/15
- [RFC v2 03/15] target/riscv: rvb: count bits set, frank . chang, 2020/12/15
- [RFC v2 04/15] target/riscv: rvb: logic-with-negate,
frank . chang <=
- [RFC v2 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/12/15
- [RFC v2 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/12/15
- [RFC v2 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/12/15
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/12/15
- [RFC v2 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/12/15