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[PATCH v2 08/12] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH v2 08/12] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 |
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Date: |
Wed, 16 Dec 2020 17:27:40 +0100 |
The MIPS ISA release '1' is common to 32/64-bit CPUs.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/mips-defs.h | 4 +--
target/mips/translate.c | 54 ++++++++++++++++++++---------------------
3 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 97899dbd3c8..f71c617a1fe 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -365,7 +365,7 @@ static inline void compute_hflags(CPUMIPSState *env)
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
- } else if (env->insn_flags & ISA_MIPS32) {
+ } else if (env->insn_flags & ISA_MIPS_R1) {
if (env->hflags & MIPS_HFLAG_64) {
env->hflags |= MIPS_HFLAG_COP1X;
}
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index df2ffae5718..31c02cc20ef 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -22,7 +22,7 @@
#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
-#define ISA_MIPS32 0x0000000000000020ULL
+#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
@@ -72,7 +72,7 @@
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
/* MIPS Technologies "Release 1" */
-#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
+#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS_R1)
#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32)
/* MIPS Technologies "Release 2" */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f32b5ebdd7e..62825dba2fd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7006,7 +7006,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
switch (reg) {
@@ -7774,7 +7774,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -8538,7 +8538,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
switch (reg) {
@@ -9264,7 +9264,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -10601,7 +10601,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext
*ctx, uint32_t opc,
break;
case OPC_DERET:
opn = "deret";
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
if ((ctx->insn_flags & ISA_MIPS32R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
@@ -10616,7 +10616,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext
*ctx, uint32_t opc,
break;
case OPC_WAIT:
opn = "wait";
- check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if ((ctx->insn_flags & ISA_MIPS32R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
goto die;
@@ -10651,7 +10651,7 @@ static void gen_compute_branch1(DisasContext *ctx,
uint32_t op,
}
if (cc != 0) {
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
}
btarget = ctx->base.pc_next + 4 + offset;
@@ -14020,7 +14020,7 @@ static int decode_extended_mips16_opc(CPUMIPSState
*env, DisasContext *ctx)
gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm);
break;
case I8_SVRS:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
{
int xsregs = (ctx->opcode >> 24) & 0x7;
int aregs = (ctx->opcode >> 16) & 0xf;
@@ -14270,7 +14270,7 @@ static int decode_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
((int8_t)ctx->opcode) << 3);
break;
case I8_SVRS:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
{
int do_ra = ctx->opcode & (1 << 6);
int do_s0 = ctx->opcode & (1 << 5);
@@ -14414,7 +14414,7 @@ static int decode_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
int ra = (ctx->opcode >> 5) & 0x1;
if (nd) {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
}
if (link) {
@@ -14435,7 +14435,7 @@ static int decode_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
@@ -14486,7 +14486,7 @@ static int decode_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_HILO(ctx, OPC_MFHI, 0, rx);
break;
case RR_CNVT:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
switch (cnvt_op) {
case RR_RY_CNVT_ZEB:
tcg_gen_ext8u_tl(cpu_gpr[rx], cpu_gpr[rx]);
@@ -14502,12 +14502,12 @@ static int decode_mips16_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
#if defined(TARGET_MIPS64)
case RR_RY_CNVT_ZEW:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
case RR_RY_CNVT_SEW:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
@@ -15426,7 +15426,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
@@ -15770,7 +15770,7 @@ static void gen_pool32axf(CPUMIPSState *env,
DisasContext *ctx, int rt, int rs)
case CLZ:
mips32_op = OPC_CLZ;
do_cl:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_cl(ctx, mips32_op, rt, rs);
break;
case RDHWR:
@@ -15797,7 +15797,7 @@ static void gen_pool32axf(CPUMIPSState *env,
DisasContext *ctx, int rt, int rs)
mips32_op = OPC_DIVU;
goto do_div;
do_div:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
case MADD:
@@ -15816,7 +15816,7 @@ static void gen_pool32axf(CPUMIPSState *env,
DisasContext *ctx, int rt, int rs)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_MSUBU;
do_mul:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, mips32_op, 0, rs, rt);
break;
default:
@@ -15964,7 +15964,7 @@ static void gen_pool32axf(CPUMIPSState *env,
DisasContext *ctx, int rt, int rs)
if (is_uhi(extract32(ctx->opcode, 16, 10))) {
gen_helper_do_semihosting(cpu_env);
} else {
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_SBRI) {
gen_reserved_instruction(ctx);
} else {
@@ -24482,7 +24482,7 @@ static void decode_opc_special_legacy(CPUMIPSState
*env, DisasContext *ctx)
switch (op1) {
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 |
INSN_LOONGSON2E | INSN_LOONGSON2F);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
@@ -24495,7 +24495,7 @@ static void decode_opc_special_legacy(CPUMIPSState
*env, DisasContext *ctx)
gen_HILO(ctx, op1, rd & 3, rs);
break;
case OPC_MOVCI:
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7,
@@ -27168,7 +27168,7 @@ static void decode_opc_special2_legacy(CPUMIPSState
*env, DisasContext *ctx)
case OPC_MADDU:
case OPC_MSUB:
case OPC_MSUBU:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
case OPC_MUL:
@@ -27185,7 +27185,7 @@ static void decode_opc_special2_legacy(CPUMIPSState
*env, DisasContext *ctx)
break;
case OPC_CLO:
case OPC_CLZ:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
gen_cl(ctx, op1, rd, rs);
break;
case OPC_SDBBP:
@@ -27196,14 +27196,14 @@ static void decode_opc_special2_legacy(CPUMIPSState
*env, DisasContext *ctx)
* XXX: not clear which exception should be raised
* when in debug mode...
*/
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
generate_exception_end(ctx, EXCP_DBp);
}
break;
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case OPC_DCLZ:
- check_insn(ctx, ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS_R1);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
@@ -28643,7 +28643,7 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
case OPC_CACHE:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_cp0_enabled(ctx);
- check_insn(ctx, ISA_MIPS3 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS3 | ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
gen_cache_operation(ctx, rt, rs, imm);
}
@@ -28654,7 +28654,7 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
/* Treat as NOP. */
} else {
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1);
/* Treat as NOP. */
}
break;
--
2.26.2
- [PATCH v2 03/12] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1, (continued)
- [PATCH v2 03/12] target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1, Philippe Mathieu-Daudé, 2020/12/16
- [PATCH v2 04/12] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2, Philippe Mathieu-Daudé, 2020/12/16
- [PATCH v2 05/12] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3, Philippe Mathieu-Daudé, 2020/12/16
- [PATCH v2 07/12] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6, Philippe Mathieu-Daudé, 2020/12/16
- [PATCH v2 06/12] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5, Philippe Mathieu-Daudé, 2020/12/16
- [PATCH v2 08/12] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1,
Philippe Mathieu-Daudé <=
- [PATCH v2 10/12] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3, Philippe Mathieu-Daudé, 2020/12/16
- [PATCH v2 09/12] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2, Philippe Mathieu-Daudé, 2020/12/16
- [PATCH v2 11/12] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5, Philippe Mathieu-Daudé, 2020/12/16
- [PATCH v2 12/12] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6, Philippe Mathieu-Daudé, 2020/12/16