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[PATCH 11/18] target/arm: do S1_ptw_translate() before address space loo
From: |
remi . denis . courmont |
Subject: |
[PATCH 11/18] target/arm: do S1_ptw_translate() before address space lookup |
Date: |
Fri, 18 Dec 2020 12:37:52 +0200 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
In the secure stage 2 translation regime, the VSTCR.SW and VTCR.NSW
bits can invert the secure flag for pagetable walks. This patchset
allows S1_ptw_translate() to change the non-secure bit.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 649c9237ce..4b6ffcd326 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10396,7 +10396,7 @@ static bool get_level1_table_address(CPUARMState *env,
ARMMMUIdx mmu_idx,
/* Translate a S1 pagetable walk through S2 if needed. */
static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
- hwaddr addr, MemTxAttrs txattrs,
+ hwaddr addr, bool *is_secure,
ARMMMUFaultInfo *fi)
{
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
@@ -10406,6 +10406,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env,
ARMMMUIdx mmu_idx,
int s2prot;
int ret;
ARMCacheAttrs cacheattrs = {};
+ MemTxAttrs txattrs = {};
+
+ assert(!*is_secure); /* TODO: S-EL2 */
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
false,
@@ -10446,9 +10449,9 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr,
bool is_secure,
AddressSpace *as;
uint32_t data;
+ addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
attrs.secure = is_secure;
as = arm_addressspace(cs, attrs);
- addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
if (fi->s1ptw) {
return 0;
}
@@ -10475,9 +10478,9 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr,
bool is_secure,
AddressSpace *as;
uint64_t data;
+ addr = S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi);
attrs.secure = is_secure;
as = arm_addressspace(cs, attrs);
- addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi);
if (fi->s1ptw) {
return 0;
}
--
2.29.2
- [PATCH 03/18] target/arm: use arm_is_el2_enabled() where applicable, (continued)
- [PATCH 03/18] target/arm: use arm_is_el2_enabled() where applicable, remi . denis . courmont, 2020/12/18
- [PATCH 06/18] target/arm: declare new AA64PFR0 bit-fields, remi . denis . courmont, 2020/12/18
- [PATCH 07/18] target/arm: add 64-bit S-EL2 to EL exception table, remi . denis . courmont, 2020/12/18
- [PATCH 04/18] target/arm: use arm_hcr_el2_eff() where applicable, remi . denis . courmont, 2020/12/18
- [PATCH 09/18] target/arm: add ARMv8.4-SEL2 system registers, remi . denis . courmont, 2020/12/18
- [PATCH 10/18] target/arm: handle VMID change in secure state, remi . denis . courmont, 2020/12/18
- [PATCH 08/18] target/arm: add MMU stage 1 for Secure EL2, remi . denis . courmont, 2020/12/18
- [PATCH 13/18] target/arm: generalize 2-stage page-walk condition, remi . denis . courmont, 2020/12/18
- [PATCH 15/18] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, remi . denis . courmont, 2020/12/18
- [PATCH 11/18] target/arm: do S1_ptw_translate() before address space lookup,
remi . denis . courmont <=
- [PATCH 12/18] target/arm: translate NS bit in page-walks, remi . denis . courmont, 2020/12/18
- [PATCH 14/18] target/arm: secure stage 2 translation regime, remi . denis . courmont, 2020/12/18
- [PATCH 16/18] target/arm: add ARMv8.4-SEL2 extension, remi . denis . courmont, 2020/12/18
- [PATCH 18/18] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2020/12/18
- [PATCH 17/18] target/arm: enable Secure EL2 in max CPU, remi . denis . courmont, 2020/12/18