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[PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
From: |
Richard Henderson |
Subject: |
[PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec |
Date: |
Thu, 24 Dec 2020 14:45:11 -0800 |
NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-conset.h | 1 +
tcg/arm/tcg-target.h | 2 +-
tcg/arm/tcg-target.c.inc | 22 ++++++++++++++++++++--
3 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/tcg/arm/tcg-target-conset.h b/tcg/arm/tcg-target-conset.h
index f32bf44f8b..30a5953621 100644
--- a/tcg/arm/tcg-target-conset.h
+++ b/tcg/arm/tcg-target-conset.h
@@ -29,6 +29,7 @@ C_O1_I2(w, w, w)
C_O1_I2(w, w, wO)
C_O1_I2(w, w, wV)
C_O1_I2(w, w, wZ)
+C_O1_I3(w, w, w, w)
C_O1_I4(r, r, r, rI, rI)
C_O1_I4(r, r, rIN, rIK, 0)
C_O2_I1(r, r, l)
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index e3c533f00f..7463be8f27 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -168,7 +168,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 1
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 6e17082df2..aea3d2cf8f 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -216,6 +216,10 @@ typedef enum {
INSN_VSARI = 0xf2800010, /* VSHR.S */
INSN_VSHRI = 0xf3800010, /* VSHR.U */
+ INSN_VBSL = 0xf3100110,
+ INSN_VBIT = 0xf3200110,
+ INSN_VBIF = 0xf3300110,
+
INSN_VTST = 0xf2000810,
INSN_VDUP_G = 0xee800b10, /* VDUP (ARM core register) */
@@ -2400,7 +2404,8 @@ static int tcg_target_op_def(TCGOpcode op)
return C_O1_I2(w, w, wV);
case INDEX_op_cmp_vec:
return C_O1_I2(w, w, wZ);
-
+ case INDEX_op_bitsel_vec:
+ return C_O1_I3(w, w, w, w);
default:
g_assert_not_reached();
}
@@ -2721,7 +2726,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
{
TCGType type = vecl + TCG_TYPE_V64;
unsigned q = vecl;
- TCGArg a0, a1, a2;
+ TCGArg a0, a1, a2, a3;
int cmode, imm8;
a0 = args[0];
@@ -2872,6 +2877,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
return;
+ case INDEX_op_bitsel_vec:
+ a3 = args[3];
+ if (a0 == a3) {
+ tcg_out_vreg3(s, INSN_VBIT, q, 0, a0, a2, a1);
+ } else if (a0 == a2) {
+ tcg_out_vreg3(s, INSN_VBIF, q, 0, a0, a3, a1);
+ } else {
+ tcg_out_mov(s, type, a0, a1);
+ tcg_out_vreg3(s, INSN_VBSL, q, 0, a0, a2, a3);
+ }
+ return;
+
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
@@ -2897,6 +2914,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+ case INDEX_op_bitsel_vec:
return 1;
case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
--
2.25.1
- [PATCH 06/15] tcg/arm: Implement minimal vector operations, (continued)
- [PATCH 06/15] tcg/arm: Implement minimal vector operations, Richard Henderson, 2020/12/24
- [PATCH 08/15] tcg/arm: Implement TCG_TARGET_HAS_shi_vec, Richard Henderson, 2020/12/24
- [PATCH 11/15] tcg/arm: Implement TCG_TARGET_HAS_minmax_vec, Richard Henderson, 2020/12/24
- [PATCH 13/15] tcg/arm: Implement TCG_TARGET_HAS_shv_vec, Richard Henderson, 2020/12/24
- [PATCH 03/15] tcg/arm: Implement tcg_out_mov for vector types, Richard Henderson, 2020/12/24
- [PATCH 07/15] tcg/arm: Implement andc, orc, abs, neg, not vector operations, Richard Henderson, 2020/12/24
- [PATCH 09/15] tcg/arm: Implement TCG_TARGET_HAS_mul_vec, Richard Henderson, 2020/12/24
- [PATCH 10/15] tcg/arm: Implement TCG_TARGET_HAS_sat_vec, Richard Henderson, 2020/12/24
- [PATCH 14/15] tcg/arm: Implement TCG_TARGET_HAS_roti_vec, Richard Henderson, 2020/12/24
- [PATCH 15/15] tcg/arm: Implement TCG_TARGET_HAS_rotv_vec, Richard Henderson, 2020/12/24
- [PATCH 12/15] tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec,
Richard Henderson <=