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Re: [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support
From: |
Pragnesh Patel |
Subject: |
Re: [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support |
Date: |
Sat, 2 Jan 2021 17:56:56 +0530 |
Hi BIn,
1) Please rebase this series on master.
2) When i tried to boot from SD card image it shows below,
pragneshp:sifive-qemu$ ./build/riscv64-softmmu/qemu-system-riscv64 -M
sifive_u,msel=11 -m 4G -nographic -bios
~/opensource/u-boot/spl/u-boot-spl.bin -device
sd-card,spi=true,drive=mycard -drive
file=~/opensource/u-boot/fsbl.gpt,id=mycard,format=raw,if=none
qemu-system-riscv64: -device sd-card,spi=true,drive=mycard: Drive
'mycard' is already in use by another device
I hacked the qemu code temporary and able to boot U-Boot from SD card,
below is my hack
pragneshp:sifive-qemu$ git diff
diff --git a/block/block-backend.c b/block/block-backend.c
index ce78d30794..cfa739fa40 100644
--- a/block/block-backend.c
+++ b/block/block-backend.c
@@ -888,10 +888,11 @@ void blk_get_perm(BlockBackend *blk, uint64_t
*perm, uint64_t *shared_perm)
*/
int blk_attach_dev(BlockBackend *blk, DeviceState *dev)
{
+#if 0
if (blk->dev) {
return -EBUSY;
}
-
+#endif
After applying this hack, I was able to boot U-Boot from Sd card
Bootlogs:
pragneshp:sifive-qemu$ ./build/riscv64-softmmu/qemu-system-riscv64 -M
sifive_u,msel=11 -m 4G -nographic -bios
~/opensource/u-boot/spl/u-boot-spl.bin -device
sd-card,spi=true,drive=mycard -drive
file=~/opensource/u-boot/fsbl.gpt,id=mycard,format=raw,if=none
U-Boot SPL 2020.10-rc5-00007-gf9aadb57b1 (Dec 29 2020 - 17:48:05 +0530)
Trying to boot from MMC1
U-Boot 2020.10-rc5-00007-gf9aadb57b1 (Dec 29 2020 - 17:48:05 +0530)
CPU: rv64imafdc
Model: SiFive HiFive Unleashed A00
DRAM: 4 GiB
MMC: spi@10050000:mmc@0: 0
Loading Environment from SPIFlash... Invalid bus 0 (err=-19)
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
In: serial@10010000
Out: serial@10010000
Err: serial@10010000
Net: eth0: ethernet@10090000
Hit any key to stop autoboot: 0
=>
Thanks for the series.
On Thu, Dec 31, 2020 at 5:00 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This adds the missing SPI support to the `sifive_u` machine in the QEMU
> mainline. With this series, upstream U-Boot for the SiFive HiFive Unleashed
> board can boot on QEMU `sifive_u` out of the box. This allows users to
> develop and test the recommended RISC-V boot flow with a real world use
> case: ZSBL (in QEMU) loads U-Boot SPL from SD card or SPI flash to L2LIM,
> then U-Boot SPL loads the payload from SD card or SPI flash that is a
> combination of OpenSBI fw_dynamic firmware and U-Boot proper.
>
> The m25p80 model is updated to support ISSI flash series. A bunch of
> ssi-sd issues are fixed, and writing to SD card in SPI mode is supported.
>
> reST documentation for RISC-V is added. Currently only `sifive_u`
> machine is documented, but more to come.
>
>
> Bin Meng (22):
> hw/block: m25p80: Add ISSI SPI flash support
> hw/block: m25p80: Add various ISSI flash information
> hw/sd: ssi-sd: Fix incorrect card response sequence
> hw/sd: sd: Support CMD59 for SPI mode
> hw/sd: sd: Drop sd_crc16()
> util: Add CRC16 (CCITT) calculation routines
> hw/sd: ssi-sd: Suffix a data block with CRC16
> hw/sd: ssi-sd: Support multiple block read (CMD18)
> hw/sd: ssi-sd: Use macros for the dummy value and tokens in the
> transfer
> hw/sd: sd: Remove duplicated codes in single/multiple block read/write
> hw/sd: sd: Allow single/multiple block write for SPI mode
> hw/sd: sd.h: Cosmetic change of using spaces
> hw/sd: Introduce receive_ready() callback
> hw/sd: ssi-sd: Support single block write
> hw/sd: ssi-sd: Support multiple block write
> hw/ssi: Add SiFive SPI controller support
> hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
> hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
> hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
> docs/system: Sort targets in alphabetical order
> docs/system: Add RISC-V documentation
> docs/system: riscv: Add documentation for sifive_u machine
>
> docs/system/riscv/sifive_u.rst | 336 +++++++++++++++++++++++++++++++++
> docs/system/target-riscv.rst | 72 +++++++
> docs/system/targets.rst | 20 +-
> include/hw/riscv/sifive_u.h | 9 +-
> include/hw/sd/sd.h | 44 ++---
> include/hw/ssi/sifive_spi.h | 47 +++++
> include/qemu/crc-ccitt.h | 33 ++++
> hw/block/m25p80.c | 51 ++++-
> hw/riscv/sifive_u.c | 91 +++++++++
> hw/sd/core.c | 13 ++
> hw/sd/sd.c | 82 +-------
> hw/sd/ssi-sd.c | 127 +++++++++++--
> hw/ssi/sifive_spi.c | 290 ++++++++++++++++++++++++++++
> util/crc-ccitt.c | 127 +++++++++++++
> hw/riscv/Kconfig | 3 +
> hw/ssi/Kconfig | 4 +
> hw/ssi/meson.build | 1 +
> util/meson.build | 1 +
> 18 files changed, 1232 insertions(+), 119 deletions(-)
> create mode 100644 docs/system/riscv/sifive_u.rst
> create mode 100644 docs/system/target-riscv.rst
> create mode 100644 include/hw/ssi/sifive_spi.h
> create mode 100644 include/qemu/crc-ccitt.h
> create mode 100644 hw/ssi/sifive_spi.c
> create mode 100644 util/crc-ccitt.c
>
> --
> 2.25.1
>
>
- Re: [PATCH 00/22] hw/riscv: sifive_u: Add missing SPI support,
Pragnesh Patel <=