[PATCH v3 00/15] target/mips/mips-defs: Simplify ISA definitions

[Philippe Mathieu-Daudé]

v3: Replace ISA_MIPS3 by ISA_MIPS64 (Richard)
v2: Do not use MIPS3 for 64R1 (Jiaxun)

Missing review: 1, 3, 4, 5

As we don't need to duplicate 32/64-bit ISA defititions,
this series remove the duplicated 64-bit variants,
simplifying the overall.

Regards,

Phil.

$ git backport-diff -u v2 -r ..v3
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respective=
ly

001/15:[down] 'target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment'
002/15:[----] [--] 'target/mips/mips-defs: Reorder CPU_MIPS5 definition'
003/15:[down] 'target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPS=
xxR1'
004/15:[down] 'target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64=
bit()'
005/15:[down] 'hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()'
006/15:[0004] [FC] 'target/mips/mips-defs: Use ISA_MIPS32 definition to check=
 Release 1'
007/15:[0004] [FC] 'target/mips/mips-defs: Use ISA_MIPS32R2 definition to che=
ck Release 2'
008/15:[----] [--] 'target/mips/mips-defs: Use ISA_MIPS32R3 definition to che=
ck Release 3'
009/15:[----] [--] 'target/mips/mips-defs: Use ISA_MIPS32R5 definition to che=
ck Release 5'
010/15:[0002] [FC] 'target/mips/mips-defs: Use ISA_MIPS32R6 definition to che=
ck Release 6'
011/15:[0004] [FC] 'target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1'
012/15:[0006] [FC] 'target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2'
013/15:[----] [-C] 'target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3'
014/15:[----] [--] 'target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5'
015/15:[0018] [FC] 'target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6'

Philippe Mathieu-Daud=C3=A9 (15):
  target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
  target/mips/mips-defs: Reorder CPU_MIPS5 definition
  target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
  target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
  hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
  target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
  target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
  target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
  target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
  target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
  target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
  target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
  target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
  target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
  target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6

 target/mips/cpu.h                |   5 +
 target/mips/internal.h           |   8 +-
 target/mips/mips-defs.h          |  46 +--
 hw/mips/boston.c                 |   6 +-
 linux-user/mips/cpu_loop.c       |   6 +-
 target/mips/cp0_helper.c         |  18 +-
 target/mips/cp0_timer.c          |   4 +-
 target/mips/cpu.c                |   6 +-
 target/mips/fpu_helper.c         |   4 +-
 target/mips/helper.c             |  12 +-
 target/mips/translate.c          | 620 +++++++++++++++----------------
 target/mips/translate_init.c.inc |  14 +-
 12 files changed, 370 insertions(+), 379 deletions(-)

--=20
2.26.2