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[RFC PATCH v2 14/32] hw/pci/cxl: Create a CXL bus type
From: |
Ben Widawsky |
Subject: |
[RFC PATCH v2 14/32] hw/pci/cxl: Create a CXL bus type |
Date: |
Tue, 5 Jan 2021 08:53:05 -0800 |
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the bus to the
correct type. This is less code and useful for debugging via simply
looking at the flags.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
hw/pci-bridge/pci_expander_bridge.c | 9 ++++++++-
include/hw/pci/pci_bus.h | 7 +++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/pci-bridge/pci_expander_bridge.c
b/hw/pci-bridge/pci_expander_bridge.c
index 232b7ce305..88c45dc3b5 100644
--- a/hw/pci-bridge/pci_expander_bridge.c
+++ b/hw/pci-bridge/pci_expander_bridge.c
@@ -24,7 +24,7 @@
#include "hw/boards.h"
#include "qom/object.h"
-enum BusType { PCI, PCIE };
+enum BusType { PCI, PCIE, CXL };
#define TYPE_PXB_BUS "pxb-bus"
typedef struct PXBBus PXBBus;
@@ -35,6 +35,10 @@ DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS,
DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS,
TYPE_PXB_PCIE_BUS)
+#define TYPE_PXB_CXL_BUS "pxb-cxl-bus"
+DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS,
+ TYPE_PXB_CXL_BUS)
+
struct PXBBus {
/*< private >*/
PCIBus parent_obj;
@@ -244,6 +248,9 @@ static void pxb_dev_realize_common(PCIDevice *dev, enum
BusType type,
ds = qdev_new(TYPE_PXB_HOST);
if (type == PCIE) {
bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS);
+ } else if (type == CXL) {
+ bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS);
+ bus->flags |= PCI_BUS_CXL;
} else {
bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0,
TYPE_PXB_BUS);
bds = qdev_new("pci-bridge");
diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index 347440d42c..eb94e7e85c 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -24,6 +24,8 @@ enum PCIBusFlags {
PCI_BUS_IS_ROOT = 0x0001,
/* PCIe extended configuration space is accessible on this bus */
PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002,
+ /* This is a CXL Type BUS */
+ PCI_BUS_CXL = 0x0004,
};
struct PCIBus {
@@ -53,6 +55,11 @@ struct PCIBus {
Notifier machine_done;
};
+static inline bool pci_bus_is_cxl(PCIBus *bus)
+{
+ return !!(bus->flags & PCI_BUS_CXL);
+}
+
static inline bool pci_bus_is_root(PCIBus *bus)
{
return !!(bus->flags & PCI_BUS_IS_ROOT);
--
2.30.0
- [RFC PATCH v2 09/32] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1), (continued)
- [RFC PATCH v2 09/32] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 08/32] hw/cxl/device: Add memory devices (8.2.8.5), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 10/32] hw/cxl/device: Placeholder for firmware commands, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 11/32] hw/cxl/device: Timestamp implementation (8.2.9.3), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 13/32] hw/pxb: Use a type for realizing expanders, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 12/32] hw/cxl/device: Add log commands (8.2.9.4) + CEL, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 32/32] qtest/cxl: Add very basic sanity tests, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 30/32] tests/acpi: Add new CEDT files, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 29/32] Temp: acpi/cxl: Add ACPI0017 (CEDT awareness), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 14/32] hw/pci/cxl: Create a CXL bus type,
Ben Widawsky <=
- [RFC PATCH v2 15/32] hw/pxb: Allow creation of a CXL PXB (host bridge), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 31/32] WIP: i386/cxl: Initialize a host bridge, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 16/32] qtest: allow DSDT acpi table changes, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 18/32] tests/acpi: remove stale allowed tables, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 17/32] acpi/pci: Consolidate host bridge setup, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 19/32] hw/pci: Plumb _UID through host bridges, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 20/32] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 21/32] acpi/pxb/cxl: Reserve host bridge MMIO, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 22/32] hw/pxb/cxl: Add "windows" for host bridges, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 25/32] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Ben Widawsky, 2021/01/05