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[PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h'
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h' |
Date: |
Thu, 7 Jan 2021 23:22:19 +0100 |
Some FPU translation functions / registers can be used by
ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-15-f4bug@amsat.org>
---
target/mips/translate.h | 7 +++++++
target/mips/translate.c | 12 ++++++------
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 5f744c63374..4c30a328e4b 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -60,12 +60,19 @@ void check_insn(DisasContext *ctx, uint64_t flags);
#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
#endif
+void check_cp1_enabled(DisasContext *ctx);
void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+int get_fp_bit(int cc);
+
extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv_i32 fpu_fcr0, fpu_fcr31;
+extern TCGv_i64 fpu_f64[32];
extern TCGv bcond;
#define LOG_DISAS(...) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7c20ed33df7..610fba61de4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
-static TCGv_i32 fpu_fcr0, fpu_fcr31;
-static TCGv_i64 fpu_f64[32];
+TCGv_i32 fpu_fcr0, fpu_fcr31;
+TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
#if defined(TARGET_MIPS64)
@@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32
t, int reg)
}
}
-static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(t, fpu_f64[reg]);
@@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t,
int reg)
}
}
-static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(fpu_f64[reg], t);
@@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64
t, int reg)
}
}
-static inline int get_fp_bit(int cc)
+int get_fp_bit(int cc)
{
if (cc) {
return 24 + cc;
@@ -2907,7 +2907,7 @@ static inline void check_cp0_enabled(DisasContext *ctx)
}
}
-static inline void check_cp1_enabled(DisasContext *ctx)
+void check_cp1_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
generate_exception_err(ctx, EXCP_CpU, 1);
--
2.26.2
- [PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs, (continued)
- [PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 23/66] target/mips: Move common helpers from helper.c to cpu.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 25/66] target/mips: Fix code style for checkpatch.pl, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 28/66] target/mips/translate: Extract DisasContext structure, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 29/66] target/mips/translate: Add declarations for generic code, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 31/66] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 32/66] target/mips: Declare generic FPU functions in 'translate.h',
Philippe Mathieu-Daudé <=
- [PULL 33/66] target/mips: Extract FPU specific definitions to translate.h, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 34/66] target/mips: Only build TCG code when CONFIG_TCG is set, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 35/66] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 36/66] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 37/66] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 38/66] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 39/66] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 40/66] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 41/66] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 42/66] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2021/01/07