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[PATCH v6 25/35] Hexagon (target/hexagon) instruction classes
From: |
Taylor Simpson |
Subject: |
[PATCH v6 25/35] Hexagon (target/hexagon) instruction classes |
Date: |
Thu, 7 Jan 2021 22:28:56 -0600 |
Determine legal VLIW slots for each instruction
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/iclass.h | 50 ++++++++++++++++++++++++++
target/hexagon/iclass.c | 73 ++++++++++++++++++++++++++++++++++++++
target/hexagon/imported/iclass.def | 51 ++++++++++++++++++++++++++
3 files changed, 174 insertions(+)
create mode 100644 target/hexagon/iclass.h
create mode 100644 target/hexagon/iclass.c
create mode 100644 target/hexagon/imported/iclass.def
diff --git a/target/hexagon/iclass.h b/target/hexagon/iclass.h
new file mode 100644
index 0000000..b57f11d
--- /dev/null
+++ b/target/hexagon/iclass.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_ICLASS_H
+#define HEXAGON_ICLASS_H
+
+#include "opcodes.h"
+
+#define ICLASS_FROM_TYPE(TYPE) ICLASS_##TYPE
+
+enum {
+
+#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) ICLASS_FROM_TYPE(TYPE),
+#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) ICLASS_FROM_TYPE(TYPE),
+#include "imported/iclass.def"
+#undef DEF_PP_ICLASS32
+#undef DEF_EE_ICLASS32
+
+ ICLASS_FROM_TYPE(COPROC_VX),
+ ICLASS_FROM_TYPE(COPROC_VMEM),
+ NUM_ICLASSES
+};
+
+typedef enum {
+ SLOTS_0 = (1 << 0),
+ SLOTS_1 = (1 << 1),
+ SLOTS_2 = (1 << 2),
+ SLOTS_3 = (1 << 3),
+ SLOTS_01 = SLOTS_0 | SLOTS_1,
+ SLOTS_23 = SLOTS_2 | SLOTS_3,
+ SLOTS_0123 = SLOTS_0 | SLOTS_1 | SLOTS_2 | SLOTS_3,
+} SlotMask;
+
+extern SlotMask find_iclass_slots(Opcode opcode, int itype);
+
+#endif
diff --git a/target/hexagon/iclass.c b/target/hexagon/iclass.c
new file mode 100644
index 0000000..05117a9
--- /dev/null
+++ b/target/hexagon/iclass.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "iclass.h"
+
+static const SlotMask iclass_info[] = {
+
+#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) \
+ [ICLASS_FROM_TYPE(TYPE)] = SLOTS_##SLOTS,
+#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) \
+ [ICLASS_FROM_TYPE(TYPE)] = SLOTS_##SLOTS,
+#include "imported/iclass.def"
+#undef DEF_PP_ICLASS32
+#undef DEF_EE_ICLASS32
+};
+
+SlotMask find_iclass_slots(Opcode opcode, int itype)
+{
+ /* There are some exceptions to what the iclass dictates */
+ if (GET_ATTRIB(opcode, A_ICOP)) {
+ return SLOTS_2;
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT0ONLY)) {
+ return SLOTS_0;
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT1ONLY)) {
+ return SLOTS_1;
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT2ONLY)) {
+ return SLOTS_2;
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT3ONLY)) {
+ return SLOTS_3;
+ } else if (GET_ATTRIB(opcode, A_COF) &&
+ GET_ATTRIB(opcode, A_INDIRECT) &&
+ !GET_ATTRIB(opcode, A_MEMLIKE) &&
+ !GET_ATTRIB(opcode, A_MEMLIKE_PACKET_RULES)) {
+ return SLOTS_2;
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_NOSLOT1)) {
+ return SLOTS_0;
+ } else if ((opcode == J2_trap0) ||
+ (opcode == Y2_isync) ||
+ (opcode == J4_hintjumpr)) {
+ return SLOTS_2;
+ } else if ((itype == ICLASS_V2LDST) && (GET_ATTRIB(opcode, A_STORE))) {
+ return SLOTS_01;
+ } else if ((itype == ICLASS_V2LDST) && (!GET_ATTRIB(opcode, A_STORE))) {
+ return SLOTS_01;
+ } else if (GET_ATTRIB(opcode, A_CRSLOT23)) {
+ return SLOTS_23;
+ } else if (GET_ATTRIB(opcode, A_RESTRICT_PREFERSLOT0)) {
+ return SLOTS_0;
+ } else if (GET_ATTRIB(opcode, A_SUBINSN)) {
+ return SLOTS_01;
+ } else if (GET_ATTRIB(opcode, A_CALL)) {
+ return SLOTS_23;
+ } else if ((opcode == J4_jumpseti) || (opcode == J4_jumpsetr)) {
+ return SLOTS_23;
+ } else {
+ return iclass_info[itype];
+ }
+}
diff --git a/target/hexagon/imported/iclass.def
b/target/hexagon/imported/iclass.def
new file mode 100644
index 0000000..92b0406
--- /dev/null
+++ b/target/hexagon/imported/iclass.def
@@ -0,0 +1,51 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* DEF_*(TYPE,SLOTS,UNITS) */
+DEF_PP_ICLASS32(EXTENDER,0123,LDST|SUNIT|MUNIT) /* 0 */
+DEF_PP_ICLASS32(CJ,0123,CTRLFLOW) /* 1 */
+DEF_PP_ICLASS32(NCJ,01,LDST|CTRLFLOW) /* 2 */
+DEF_PP_ICLASS32(V4LDST,01,LDST) /* 3 */
+DEF_PP_ICLASS32(V2LDST,01,LDST) /* 4 */
+DEF_PP_ICLASS32(J,0123,CTRLFLOW) /* 5 */
+DEF_PP_ICLASS32(CR,3,SUNIT) /* 6 */
+DEF_PP_ICLASS32(ALU32_2op,0123,LDST|SUNIT|MUNIT) /* 7 */
+DEF_PP_ICLASS32(S_2op,23,SUNIT|MUNIT) /* 8 */
+DEF_PP_ICLASS32(LD,01,LDST) /* 9 */
+DEF_PP_ICLASS32(ST,01,LDST) /* 10 */
+DEF_PP_ICLASS32(ALU32_ADDI,0123,LDST|SUNIT|MUNIT) /* 11 */
+DEF_PP_ICLASS32(S_3op,23,SUNIT|MUNIT) /* 12 */
+DEF_PP_ICLASS32(ALU64,23,SUNIT|MUNIT) /* 13 */
+DEF_PP_ICLASS32(M,23,SUNIT|MUNIT) /* 14 */
+DEF_PP_ICLASS32(ALU32_3op,0123,LDST|SUNIT|MUNIT) /* 15 */
+
+DEF_EE_ICLASS32(EE0,01,INVALID) /* 0 */
+DEF_EE_ICLASS32(EE1,01,INVALID) /* 1 */
+DEF_EE_ICLASS32(EE2,01,INVALID) /* 2 */
+DEF_EE_ICLASS32(EE3,01,INVALID) /* 3 */
+DEF_EE_ICLASS32(EE4,01,INVALID) /* 4 */
+DEF_EE_ICLASS32(EE5,01,INVALID) /* 5 */
+DEF_EE_ICLASS32(EE6,01,INVALID) /* 6 */
+DEF_EE_ICLASS32(EE7,01,INVALID) /* 7 */
+DEF_EE_ICLASS32(EE8,01,INVALID) /* 8 */
+DEF_EE_ICLASS32(EE9,01,INVALID) /* 9 */
+DEF_EE_ICLASS32(EEA,01,INVALID) /* 10 */
+DEF_EE_ICLASS32(EEB,01,INVALID) /* 11 */
+DEF_EE_ICLASS32(EEC,01,INVALID) /* 12 */
+DEF_EE_ICLASS32(EED,01,INVALID) /* 13 */
+DEF_EE_ICLASS32(EEE,01,INVALID) /* 14 */
+DEF_EE_ICLASS32(EEF,01,INVALID) /* 15 */
--
2.7.4
- [PATCH v6 16/35] Hexagon (target/hexagon/conv_emu.[ch]) utility functions, (continued)
- [PATCH v6 16/35] Hexagon (target/hexagon/conv_emu.[ch]) utility functions, Taylor Simpson, 2021/01/07
- [PATCH v6 19/35] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics, Taylor Simpson, 2021/01/07
- [PATCH v6 15/35] Hexagon (target/hexagon/arch.[ch]) utility functions, Taylor Simpson, 2021/01/07
- [PATCH v6 18/35] Hexagon (target/hexagon/imported) arch import, Taylor Simpson, 2021/01/07
- [PATCH v6 20/35] Hexagon (target/hexagon) generator phase 2 - generate header files, Taylor Simpson, 2021/01/07
- [PATCH v6 22/35] Hexagon (target/hexagon) generater phase 4 - decode tree, Taylor Simpson, 2021/01/07
- [PATCH v6 23/35] Hexagon (target/hexagon) opcode data structures, Taylor Simpson, 2021/01/07
- [PATCH v6 24/35] Hexagon (target/hexagon) macros, Taylor Simpson, 2021/01/07
- [PATCH v6 27/35] Hexagon (target/hexagon) TCG for instructions with multiple definitions, Taylor Simpson, 2021/01/07
- [PATCH v6 28/35] Hexagon (target/hexagon) TCG for floating point instructions, Taylor Simpson, 2021/01/07
- [PATCH v6 25/35] Hexagon (target/hexagon) instruction classes,
Taylor Simpson <=
- [PATCH v6 32/35] Hexagon build infrastructure, Taylor Simpson, 2021/01/07
- [PATCH v6 29/35] Hexagon (target/hexagon) translation, Taylor Simpson, 2021/01/07
- [PATCH v6 33/35] Add Dockerfile for hexagon, Taylor Simpson, 2021/01/07
- [PATCH v6 31/35] Hexagon (tests/tcg/hexagon) TCG tests, Taylor Simpson, 2021/01/07
- [PATCH v6 34/35] Auto-import Docker support files, Taylor Simpson, 2021/01/07