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[PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support
From: |
frank . chang |
Subject: |
[PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support |
Date: |
Tue, 12 Jan 2021 17:38:35 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 10 +++++-----
target/riscv/cpu.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8227d7aea9d..49e78456422 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -379,7 +379,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
- int vext_version = VEXT_VERSION_0_07_1;
+ int vext_version = VEXT_VERSION_1_00_0;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -497,8 +497,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
- vext_version = VEXT_VERSION_0_07_1;
+ if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
+ vext_version = VEXT_VERSION_1_00_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
@@ -506,8 +506,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
} else {
- qemu_log("vector verison is not specified, "
- "use the default value v0.7.1\n");
+ qemu_log("vector version is not specified, "
+ "use the default value v1.0\n");
}
set_vext_version(env, vext_version);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6339e848192..b0281133e09 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -86,7 +86,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define VEXT_VERSION_0_07_1 0x00000701
+#define VEXT_VERSION_1_00_0 0x00010000
enum {
TRANSLATE_SUCCESS,
--
2.17.1
- [PATCH v6 00/72] support vector extension v1.0, frank . chang, 2021/01/12
- [PATCH v6 01/72] target/riscv: drop vector 0.7.1 and add 1.0 support,
frank . chang <=
- [PATCH v6 02/72] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/01/12
- [PATCH v6 03/72] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/01/12
- [PATCH v6 04/72] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/01/12
- [PATCH v6 05/72] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/01/12
- [PATCH v6 06/72] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/01/12