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[PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space a
From: |
Peter Maydell |
Subject: |
[PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns |
Date: |
Tue, 12 Jan 2021 16:57:41 +0000 |
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
because it moved the handling of "cp insns which are handled
by looking up the cp register in the hashtable" from after the
call to the legacy disas_xscale_insn() decode to before it,
with the result that all XScale/iWMMXt insns now UNDEF.
Update valid_cp() so that it knows that on XScale cp 0 and 1
are not standard coprocessor instructions; this will cause
the decodetree trans_ functions to ignore them, so that
execution will correctly get through to the legacy decode again.
Cc: qemu-stable@nongnu.org
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
---
target/arm/translate.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f5acd32e76a..528b93dffa2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5282,7 +5282,14 @@ static bool valid_cp(DisasContext *s, int cp)
* only cp14 and cp15 are valid, and other values aren't considered
* to be in the coprocessor-instruction space at all. v8M still
* permits coprocessors 0..7.
+ * For XScale, we must not decode the XScale cp0, cp1 space as
+ * a standard coprocessor insn, because we want to fall through to
+ * the legacy disas_xscale_insn() decoder after decodetree is done.
*/
+ if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
+ return false;
+ }
+
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
!arm_dc_feature(s, ARM_FEATURE_M)) {
return cp >= 14;
--
2.20.1
- [PULL 00/21] target-arm queue, Peter Maydell, 2021/01/12
- [PULL 02/21] target/arm: enable Small Translation tables in max CPU, Peter Maydell, 2021/01/12
- [PULL 01/21] target/arm: ARMv8.4-TTST extension, Peter Maydell, 2021/01/12
- [PULL 03/21] target/arm: fix typo in cpu.h ID_AA64PFR1 field name, Peter Maydell, 2021/01/12
- [PULL 04/21] target/arm: make ARMCPU.clidr 64-bit, Peter Maydell, 2021/01/12
- [PULL 05/21] target/arm: make ARMCPU.ctr 64-bit, Peter Maydell, 2021/01/12
- [PULL 06/21] target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h, Peter Maydell, 2021/01/12
- [PULL 07/21] target/arm: add aarch64 ID register fields to cpu.h, Peter Maydell, 2021/01/12
- [PULL 08/21] target/arm: add aarch32 ID register fields to cpu.h, Peter Maydell, 2021/01/12
- [PULL 10/21] docs: Add qemu-storage-daemon(1) manpage to meson.build, Peter Maydell, 2021/01/12
- [PULL 12/21] target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns,
Peter Maydell <=
- [PULL 13/21] hw/net/lan9118: Fix RX Status FIFO PEEK value, Peter Maydell, 2021/01/12
- [PULL 11/21] docs: Build and install all the docs in a single manual, Peter Maydell, 2021/01/12
- [PULL 09/21] ui/cocoa: Update path to docs in build tree, Peter Maydell, 2021/01/12
- [PULL 14/21] hw/net/lan9118: Add symbolic constants for register offsets, Peter Maydell, 2021/01/12
- [PULL 16/21] hw/timer: Refactor NPCM7XX Timer to use CLK clock, Peter Maydell, 2021/01/12
- [PULL 15/21] hw/misc: Add clock converter in NPCM7XX CLK module, Peter Maydell, 2021/01/12
- [PULL 18/21] hw/misc: Add a PWM module for NPCM7XX, Peter Maydell, 2021/01/12