[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[PATCH] hw/char/cadence_uart: Fixed wrong Cadence UART stop bit count re

From: Anthony Dentinger
Subject: [PATCH] hw/char/cadence_uart: Fixed wrong Cadence UART stop bit count register value.
Date: Wed, 13 Jan 2021 16:15:31 -0500

Here is a reference showing that 0x00 is the correct value:
  (page 1776, Register XUARTPS_MR_OFFSET Details, which is for a platform
  called Zynq that has a UART made by Cadence)
  (Linux driver for the Cadence UART on that Zynq platform).

Signed-off-by: Anthony Dentinger <anthony.dentinger@spacecodesign.com>
 hw/char/cadence_uart.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index c603e14012..a049ed50c4 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -93,7 +93,7 @@
 #define UART_DATA_BITS_7       (0x2 << UART_MR_CHRL_SH)
 #define UART_PARITY_ODD        (0x1 << UART_MR_PAR_SH)
 #define UART_PARITY_EVEN       (0x0 << UART_MR_PAR_SH)
-#define UART_STOP_BITS_1       (0x3 << UART_MR_NBSTOP_SH)
+#define UART_STOP_BITS_1       (0x0 << UART_MR_NBSTOP_SH)
 #define UART_STOP_BITS_2       (0x2 << UART_MR_NBSTOP_SH)
 #define NORMAL_MODE            (0x0 << UART_MR_CHMODE_SH)
 #define ECHO_MODE              (0x1 << UART_MR_CHMODE_SH)

reply via email to

[Prev in Thread] Current Thread [Next in Thread]