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[PULL v2 68/69] target/mips: Remove vendor specific CPU definitions
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL v2 68/69] target/mips: Remove vendor specific CPU definitions |
Date: |
Thu, 14 Jan 2021 17:20:16 +0100 |
Vendor specific CPU definitions are not very useful. Use the
ISA definitions instead, which are more helpful when looking
at the various CPU definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-4-f4bug@amsat.org>
---
target/mips/mips-defs.h | 5 -----
target/mips/cpu-defs.c.inc | 12 +++++++-----
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 3704db85532..0a12d982a72 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -60,9 +60,6 @@
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
-#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
-#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
-#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
#define CPU_MIPS64 (ISA_MIPS3)
@@ -86,8 +83,6 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
-#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
-
/*
* Strictly follow the architecture standard:
* - Disallow "special" instruction handling for PMON/SPIM.
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 9f7bac87932..e03b2a998cd 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -531,7 +531,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 32,
- .insn_flags = CPU_VR54XX,
+ .insn_flags = CPU_MIPS4 | INSN_VR54XX,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -781,7 +781,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 40,
- .insn_flags = CPU_LOONGSON2E,
+ .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -801,7 +801,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 40,
- .insn_flags = CPU_LOONGSON2F,
+ .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -830,7 +830,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A,
+ .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
+ ASE_LMMI | ASE_LEXT,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -887,7 +888,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A,
+ .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
+ ASE_LMMI | ASE_LEXT,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2
- [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE, (continued)
- [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 66/69] target/mips: Remove CPU_R5900 definition, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition, Philippe Mathieu-Daudé, 2021/01/14
- [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions,
Philippe Mathieu-Daudé <=
- Re: [PULL v2 00/69] MIPS patches for 2021-01-14, Peter Maydell, 2021/01/15