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Re: Emulation for riscv

From: Palmer Dabbelt
Subject: Re: Emulation for riscv
Date: Thu, 14 Jan 2021 11:16:12 -0800 (PST)

On Thu, 14 Jan 2021 01:49:40 PST (-0800), bmeng.cn@gmail.com wrote:
On Thu, Jan 14, 2021 at 8:09 AM Alistair Francis <alistair23@gmail.com> wrote:

On Fri, Nov 6, 2020 at 2:36 AM Alex Bennée <alex.bennee@linaro.org> wrote:
> Palmer Dabbelt <palmer@dabbelt.com> writes:
> > On Thu, 22 Oct 2020 17:56:38 PDT (-0700), alistair23@gmail.com wrote:
> >> On Thu, Oct 22, 2020 at 4:58 PM Moises Arreola <moyarrezam@gmail.com> 
> >>>
> >>> Hello everyone, my name is Moses and I'm trying to set up a VM for a 
risc-v processor, I'm using the Risc-V Getting Started Guide and on the final step I'm 
getting an error while trying to launch the virtual machine using the cmd:
> >>
> >> Hello,
> >>
> >> Please don't use the RISC-V Getting Started Guide. Pretty much all of
> >> the information there is out of date and wrong. Unfortunately we are
> >> unable to correct it.
> >>
> >> The QEMU wiki is a much better place for information:
> >> https://wiki.qemu.org/Documentation/Platforms/RISCV
> >
> > Ya, everything at riscv.org is useless.  It's best to stick to the open 
> > documentation, as when that gets out of date we can at least fix it.  Using 
> > distro helps a lot here, the wiki describes how to run a handful of popular
> > ones that were ported to RISC-V early but if your favorite isn't on the list
> > then it may have its own documentation somewhere else.
> Even better if you could submit some .rst pages for QEMU's git:
>   docs/system/target-riscv.rst
>   docs/system/riscv/virt.rst (and maybe the other models)
> then we could improve the user manual where RiscV is currently a little
> under-represented. A number of the systems have simple example command
> lines or explain the kernel support needed for the model.

Thanks for pointing that out Alex. Bin has sent some patches for this
so RISC-V should have a presence soon.

Yep, after the initial patches are merged, we can start adding more
RISC-V docs in reST.

Thanks for doing this!

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