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[PATCH v2 16/22] tcg/mips: Split out constraint sets to tcg-target-con-s
From: |
Richard Henderson |
Subject: |
[PATCH v2 16/22] tcg/mips: Split out constraint sets to tcg-target-con-set.h |
Date: |
Fri, 15 Jan 2021 11:04:50 -1000 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target-con-set.h | 36 +++++++++++++
tcg/mips/tcg-target.h | 1 +
tcg/mips/tcg-target.c.inc | 96 +++++++++++------------------------
3 files changed, 66 insertions(+), 67 deletions(-)
create mode 100644 tcg/mips/tcg-target-con-set.h
diff --git a/tcg/mips/tcg-target-con-set.h b/tcg/mips/tcg-target-con-set.h
new file mode 100644
index 0000000000..fe3e868a2f
--- /dev/null
+++ b/tcg/mips/tcg-target-con-set.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define MIPS target-specific constraint sets.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
+ * Each operand should be a sequence of constraint letters as defined by
+ * tcg-target-con-str.h; the constraint combination is inclusive or.
+ */
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I2(SZ, S)
+C_O0_I3(SZ, S, S)
+C_O0_I3(SZ, SZ, S)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O0_I4(SZ, SZ, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rJ)
+C_O1_I2(r, r, rWZ)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, 0)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, rZ, rZ, rN, rN)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c2c32fb38f..e520a9d6e3 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -207,5 +207,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t,
uintptr_t, uintptr_t);
#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
#endif
+#define TCG_TARGET_CON_SET_H
#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 61e8740012..c93ddbe6b1 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2107,52 +2107,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
}
}
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
- static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
- static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
- static const TCGTargetOpDef SZ_SZ_S
- = { .args_ct_str = { "SZ", "SZ", "S" } };
- static const TCGTargetOpDef SZ_SZ_S_S
- = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
- static const TCGTargetOpDef r_rZ_rN
- = { .args_ct_str = { "r", "rZ", "rN" } };
- static const TCGTargetOpDef r_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_rIK
- = { .args_ct_str = { "r", "r", "rIK" } };
- static const TCGTargetOpDef r_r_rWZ
- = { .args_ct_str = { "r", "r", "rWZ" } };
- static const TCGTargetOpDef r_r_r_r
- = { .args_ct_str = { "r", "r", "r", "r" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
- static const TCGTargetOpDef movc_r6
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -2185,7 +2144,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_extract_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
@@ -2194,14 +2153,14 @@ static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode op)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
- return &r_r_rJ;
+ return C_O1_I2(r, r, rJ);
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- return &r_rZ_rN;
+ return C_O1_I2(r, rZ, rN);
case INDEX_op_mul_i32:
case INDEX_op_mulsh_i32:
case INDEX_op_muluh_i32:
@@ -2220,20 +2179,20 @@ static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode op)
case INDEX_op_remu_i64:
case INDEX_op_nor_i64:
case INDEX_op_setcond_i64:
- return &r_rZ_rZ;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_muls2_i32:
case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i64:
case INDEX_op_mulu2_i64:
- return &r_r_r_r;
+ return C_O2_I2(r, r, r, r);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
- return &r_r_rIK;
+ return C_O1_I2(r, r, rIK);
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
@@ -2244,44 +2203,47 @@ static const TCGTargetOpDef
*tcg_target_op_def(TCGOpcode op)
case INDEX_op_sar_i64:
case INDEX_op_rotr_i64:
case INDEX_op_rotl_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
- return &r_r_rWZ;
+ return C_O1_I2(r, r, rWZ);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &rZ_rZ;
+ return C_O0_I2(rZ, rZ);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- return use_mips32r6_instructions ? &movc_r6 : &movc;
-
+ return (use_mips32r6_instructions
+ ? C_O1_I4(r, rZ, rZ, rZ, rZ)
+ : C_O1_I4(r, rZ, rZ, rZ, 0));
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- return &add2;
+ return C_O2_I4(r, r, rZ, rZ, rN, rN);
case INDEX_op_setcond2_i32:
- return &setc2;
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
case INDEX_op_brcond2_i32:
- return &br2;
+ return C_O0_I4(rZ, rZ, rZ, rZ);
case INDEX_op_qemu_ld_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &r_L : &r_L_L);
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
case INDEX_op_qemu_st_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &SZ_S : &SZ_S_S);
+ ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
- : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
+ : C_O0_I4(SZ, SZ, S, S));
default:
- return NULL;
+ g_assert_not_reached();
}
}
--
2.25.1
- [PATCH v2 10/22] tcg/s390: Split out target constraints to tcg-target-con-str.h, (continued)
- [PATCH v2 10/22] tcg/s390: Split out target constraints to tcg-target-con-str.h, Richard Henderson, 2021/01/15
- [PATCH v2 12/22] tcg: Remove TCG_TARGET_CON_STR_H, Richard Henderson, 2021/01/15
- [PATCH v2 13/22] tcg/i386: Split out constraint sets to tcg-target-con-set.h, Richard Henderson, 2021/01/15
- [PATCH v2 14/22] tcg/aarch64: Split out constraint sets to tcg-target-con-set.h, Richard Henderson, 2021/01/15
- [PATCH v2 15/22] tcg/arm: Split out constraint sets to tcg-target-con-set.h, Richard Henderson, 2021/01/15
- [PATCH v2 16/22] tcg/mips: Split out constraint sets to tcg-target-con-set.h,
Richard Henderson <=
- [PATCH v2 18/22] tcg/riscv: Split out constraint sets to tcg-target-con-set.h, Richard Henderson, 2021/01/15
- [PATCH v2 17/22] tcg/ppc: Split out constraint sets to tcg-target-con-set.h, Richard Henderson, 2021/01/15
- [PATCH v2 20/22] tcg/sparc: Split out constraint sets to tcg-target-con-set.h, Richard Henderson, 2021/01/15
- [PATCH v2 19/22] tcg/s390: Split out constraint sets to tcg-target-con-set.h, Richard Henderson, 2021/01/15
- [PATCH v2 22/22] tcg: Remove TCG_TARGET_CON_SET_H, Richard Henderson, 2021/01/15