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[PATCH v2 07/12] hw/block/nvme: remove redundant zeroing of PMR register
From: |
Klaus Jensen |
Subject: |
[PATCH v2 07/12] hw/block/nvme: remove redundant zeroing of PMR registers |
Date: |
Mon, 18 Jan 2021 10:47:00 +0100 |
From: Klaus Jensen <k.jensen@samsung.com>
The controller registers are initially zero. Remove the redundant
zeroing.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/block/nvme.c | 35 -----------------------------------
1 file changed, 35 deletions(-)
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index f3bea582b3c0..9ee9570bb65c 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -4179,43 +4179,8 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice
*pci_dev)
static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
{
- /* PMR Capabities register */
- n->bar.pmrcap = 0;
- NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
- NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
- NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
- /* Turn on bit 1 support */
NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
- NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
- NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
-
- /* PMR Control register */
- n->bar.pmrctl = 0;
- NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
-
- /* PMR Status register */
- n->bar.pmrsts = 0;
- NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
- NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
-
- /* PMR Elasticity Buffer Size register */
- n->bar.pmrebs = 0;
- NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
- NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
- NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
-
- /* PMR Sustained Write Throughput register */
- n->bar.pmrswtp = 0;
- NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
- NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
-
- /* PMR Memory Space Control register */
- n->bar.pmrmsc = 0;
- NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
- NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
PCI_BASE_ADDRESS_SPACE_MEMORY |
--
2.30.0
- Re: [PATCH v2 02/12] hw/block/nvme: fix 64 bit register hi/lo split writes, (continued)
[PATCH v2 03/12] hw/block/nvme: indicate CMB support through controller capabilities register, Klaus Jensen, 2021/01/18
[PATCH v2 04/12] hw/block/nvme: move msix table and pba to BAR 0, Klaus Jensen, 2021/01/18
[PATCH v2 05/12] hw/block/nvme: allow cmb and pmr to coexist, Klaus Jensen, 2021/01/18
[PATCH v2 06/12] hw/block/nvme: rename PMR/CMB shift/mask fields, Klaus Jensen, 2021/01/18
[PATCH v2 07/12] hw/block/nvme: remove redundant zeroing of PMR registers,
Klaus Jensen <=
[PATCH v2 08/12] hw/block/nvme: disable PMR at boot up, Klaus Jensen, 2021/01/18
[PATCH v2 09/12] hw/block/nvme: add PMR RDS/WDS support, Klaus Jensen, 2021/01/18
[PATCH v2 10/12] hw/block/nvme: move cmb logic to v1.4, Klaus Jensen, 2021/01/18