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[PULL 16/33] target/arm: generalize 2-stage page-walk condition
From: |
Peter Maydell |
Subject: |
[PULL 16/33] target/arm: generalize 2-stage page-walk condition |
Date: |
Tue, 19 Jan 2021 15:10:47 +0000 |
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
The stage_1_mmu_idx() already effectively keeps track of which
translation regimes have two stages. Don't hard-code another test.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-13-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 521f85a695a..75166a21583 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12160,11 +12160,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong
address,
target_ulong *page_size,
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
{
- if (mmu_idx == ARMMMUIdx_E10_0 ||
- mmu_idx == ARMMMUIdx_E10_1 ||
- mmu_idx == ARMMMUIdx_E10_1_PAN) {
+ ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
+
+ if (mmu_idx != s1_mmu_idx) {
/* Call ourselves recursively to do the stage 1 and then stage 2
- * translations.
+ * translations if mmu_idx is a two-stage regime.
*/
if (arm_feature(env, ARM_FEATURE_EL2)) {
hwaddr ipa;
@@ -12172,9 +12172,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong
address,
int ret;
ARMCacheAttrs cacheattrs2 = {};
- ret = get_phys_addr(env, address, access_type,
- stage_1_mmu_idx(mmu_idx), &ipa, attrs,
- prot, page_size, fi, cacheattrs);
+ ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
+ attrs, prot, page_size, fi, cacheattrs);
/* If S1 fails or S2 is disabled, return early. */
if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
--
2.20.1
- [PULL 04/33] target/arm: remove redundant tests, (continued)
- [PULL 04/33] target/arm: remove redundant tests, Peter Maydell, 2021/01/19
- [PULL 11/33] target/arm: add MMU stage 1 for Secure EL2, Peter Maydell, 2021/01/19
- [PULL 08/33] target/arm: factor MDCR_EL2 common handling, Peter Maydell, 2021/01/19
- [PULL 13/33] target/arm: handle VMID change in secure state, Peter Maydell, 2021/01/19
- [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table, Peter Maydell, 2021/01/19
- [PULL 15/33] target/arm: translate NS bit in page-walks, Peter Maydell, 2021/01/19
- [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers, Peter Maydell, 2021/01/19
- [PULL 17/33] target/arm: secure stage 2 translation regime, Peter Maydell, 2021/01/19
- [PULL 21/33] target/arm: enable Secure EL2 in max CPU, Peter Maydell, 2021/01/19
- [PULL 14/33] target/arm: do S1_ptw_translate() before address space lookup, Peter Maydell, 2021/01/19
- [PULL 16/33] target/arm: generalize 2-stage page-walk condition,
Peter Maydell <=
- [PULL 18/33] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, Peter Maydell, 2021/01/19
- [PULL 22/33] target/arm: refactor vae1_tlbmask(), Peter Maydell, 2021/01/19
- [PULL 24/33] target/arm: Update PFIRST, PNEXT for pred_desc, Peter Maydell, 2021/01/19
- [PULL 25/33] target/arm: Update ZIP, UZP, TRN for pred_desc, Peter Maydell, 2021/01/19
- [PULL 23/33] target/arm: Introduce PREDDESC field definitions, Peter Maydell, 2021/01/19
- [PULL 20/33] target/arm: Implement SCR_EL2.EEL2, Peter Maydell, 2021/01/19
- [PULL 19/33] target/arm: revector to run-time pick target EL, Peter Maydell, 2021/01/19
- [PULL 27/33] hw/misc/pvpanic: split-out generic and bus dependent code, Peter Maydell, 2021/01/19
- [PULL 28/33] hw/misc/pvpanic: add PCI interface support, Peter Maydell, 2021/01/19
- [PULL 26/33] target/arm: Update REV, PUNPK for pred_desc, Peter Maydell, 2021/01/19