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Re: [PATCH v3 00/12] hw/block/nvme: misc cmb/pmr patches and bump to v1.

From: Keith Busch
Subject: Re: [PATCH v3 00/12] hw/block/nvme: misc cmb/pmr patches and bump to v1.4
Date: Wed, 20 Jan 2021 09:20:07 +0900
User-agent: Mutt/1.12.1 (2019-06-15)

On Tue, Jan 19, 2021 at 11:14:52AM +0100, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
> This is a resend of "hw/block/nvme: allow cmb and pmr to coexist" with
> some more PMR work added (PMR RDS/WDS support).
> This includes a resurrection of Andrzej's series[1] from back July.
> Andrzej's main patch basically moved the CMB from BAR 2 into an offset
> in BAR 4 (located after the MSI-X table and PBA). Having an offset on
> the CMB causes a bunch of calculations related to address mapping to
> change.
> So, since I couldn't get the patch to apply cleanly I took a stab at
> implementing the suggestion I originally came up with: simply move the
> MSI-X table and PBA from BAR 4 into BAR 0 (up-aligned to a 4 KiB
> boundary after the main NVMe controller registers). This way we can keep
> the CMB at offset zero in its own BAR and free up BAR 4 for use by PMR.
> This makes the patch simpler and does not impact any of the existing
> address mapping code.
>   [1]: 
> https://lore.kernel.org/qemu-devel/20200729220107.37758-1-andrzej.jakowski@linux.intel.com/


Series looks good to me.

Reviewed-by: Keith Busch <kbusch@kernel.org>

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