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[PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not te
From: |
Richard Henderson |
Subject: |
[PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps |
Date: |
Fri, 5 Feb 2021 12:56:07 -1000 |
Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd
argument is an integer, not a temporary, which now tickles
an assert added in e89b28a6350.
Previously, the value computed into v2 would be garbage for
rotli_vec, but as the value was unused it caused no harm.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 3c1ee39fd4..1376cdc404 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2488,7 +2488,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
v0 = temp_tcgv_vec(arg_temp(a0));
v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
a2 = va_arg(va, TCGArg);
- v2 = temp_tcgv_vec(arg_temp(a2));
+ va_end(va);
switch (opc) {
case INDEX_op_rotli_vec:
@@ -2502,6 +2502,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
/* Right shifts are negative left shifts for AArch64. */
+ v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
tcg_gen_neg_vec(vece, t1, v2);
opc = (opc == INDEX_op_shrv_vec
@@ -2512,6 +2513,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
break;
case INDEX_op_rotlv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
c1 = tcg_constant_vec(type, vece, 8 << vece);
tcg_gen_sub_vec(vece, t1, v2, c1);
@@ -2525,6 +2527,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
break;
case INDEX_op_rotrv_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
t1 = tcg_temp_new_vec(type);
t2 = tcg_temp_new_vec(type);
c1 = tcg_constant_vec(type, vece, 8 << vece);
@@ -2543,8 +2546,6 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type,
unsigned vece,
default:
g_assert_not_reached();
}
-
- va_end(va);
}
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
--
2.25.1
- [PULL 00/46] tcg patch queue, Richard Henderson, 2021/02/05
- [PULL 01/46] tcg/s390: Fix compare instruction from extended-immediate facility, Richard Henderson, 2021/02/05
- [PULL 02/46] exec/cpu-defs: Remove TCG backends dependency, Richard Henderson, 2021/02/05
- [PULL 03/46] tcg/aarch64: Do not convert TCGArg to temps that are not temps,
Richard Henderson <=
- [PULL 04/46] configure: Fix --enable-tcg-interpreter, Richard Henderson, 2021/02/05
- [PULL 05/46] tcg/tci: Make tci_tb_ptr thread-local, Richard Henderson, 2021/02/05
- [PULL 06/46] tcg/tci: Implement INDEX_op_ld16s_i32, Richard Henderson, 2021/02/05
- [PULL 07/46] tcg/tci: Implement INDEX_op_ld8s_i64, Richard Henderson, 2021/02/05
- [PULL 08/46] tcg/tci: Inline tci_write_reg32s into the only caller, Richard Henderson, 2021/02/05
- [PULL 09/46] tcg/tci: Inline tci_write_reg8 into its callers, Richard Henderson, 2021/02/05
- [PULL 10/46] tcg/tci: Inline tci_write_reg16 into the only caller, Richard Henderson, 2021/02/05
- [PULL 11/46] tcg/tci: Inline tci_write_reg32 into all callers, Richard Henderson, 2021/02/05
- [PULL 12/46] tcg/tci: Inline tci_write_reg64 into 64-bit callers, Richard Henderson, 2021/02/05
- [PULL 13/46] tcg/tci: Merge INDEX_op_ld8u_{i32,i64}, Richard Henderson, 2021/02/05