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[PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16
From: |
Richard Henderson |
Subject: |
[PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16 |
Date: |
Fri, 5 Feb 2021 12:56:30 -1000 |
As noted in several comments, 8 regs is not enough for 32-bit
to perform calls, as currently implemented. Shortly, we will
rearrange the encoding which will make 32 regs impossible.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 32 +++++---------------------------
tcg/tci/tcg-target.c.inc | 26 --------------------------
2 files changed, 5 insertions(+), 53 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 7fc349a3de..8f7ed676fc 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -133,11 +133,8 @@
#define TCG_TARGET_HAS_mulu2_i32 1
#endif /* TCG_TARGET_REG_BITS == 64 */
-/* Number of registers available.
- For 32 bit hosts, we need more than 8 registers (call arguments). */
-/* #define TCG_TARGET_NB_REGS 8 */
+/* Number of registers available. */
#define TCG_TARGET_NB_REGS 16
-/* #define TCG_TARGET_NB_REGS 32 */
/* List of registers which are used by TCG. */
typedef enum {
@@ -149,7 +146,6 @@ typedef enum {
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
@@ -158,33 +154,15 @@ typedef enum {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
-#if TCG_TARGET_NB_REGS >= 32
- TCG_REG_R16,
- TCG_REG_R17,
- TCG_REG_R18,
- TCG_REG_R19,
- TCG_REG_R20,
- TCG_REG_R21,
- TCG_REG_R22,
- TCG_REG_R23,
- TCG_REG_R24,
- TCG_REG_R25,
- TCG_REG_R26,
- TCG_REG_R27,
- TCG_REG_R28,
- TCG_REG_R29,
- TCG_REG_R30,
- TCG_REG_R31,
-#endif
-#endif
+
+ TCG_AREG0 = TCG_REG_R14,
+ TCG_REG_CALL_STACK = TCG_REG_R15,
+
/* Special value UINT8_MAX is used by TCI to encode constant values. */
TCG_CONST = UINT8_MAX
} TCGReg;
-#define TCG_AREG0 (TCG_TARGET_NB_REGS - 2)
-
/* Used for function call generation. */
-#define TCG_REG_CALL_STACK (TCG_TARGET_NB_REGS - 1)
#define TCG_TARGET_CALL_STACK_OFFSET 0
#define TCG_TARGET_STACK_ALIGN 16
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 3327ce3072..7e3bed811e 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -187,7 +187,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
@@ -196,7 +195,6 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
-#endif
};
#if MAX_OPC_PARAM_IARGS != 6
@@ -216,15 +214,11 @@ static const int tcg_target_call_iarg_regs[] = {
#if TCG_TARGET_REG_BITS == 32
/* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
TCG_REG_R7,
-#if TCG_TARGET_NB_REGS >= 16
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10,
TCG_REG_R11,
TCG_REG_R12,
-#else
-# error Too few input registers available
-#endif
#endif
};
@@ -245,7 +239,6 @@ static const char *const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"r05",
"r06",
"r07",
-#if TCG_TARGET_NB_REGS >= 16
"r08",
"r09",
"r10",
@@ -254,25 +247,6 @@ static const char *const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"r13",
"r14",
"r15",
-#if TCG_TARGET_NB_REGS >= 32
- "r16",
- "r17",
- "r18",
- "r19",
- "r20",
- "r21",
- "r22",
- "r23",
- "r24",
- "r25",
- "r26",
- "r27",
- "r28",
- "r29",
- "r30",
- "r31"
-#endif
-#endif
};
#endif
--
2.25.1
- [PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64}, (continued)
- [PULL 14/46] tcg/tci: Merge INDEX_op_ld8s_{i32,i64}, Richard Henderson, 2021/02/05
- [PULL 15/46] tcg/tci: Merge INDEX_op_ld16u_{i32,i64}, Richard Henderson, 2021/02/05
- [PULL 16/46] tcg/tci: Merge INDEX_op_ld16s_{i32,i64}, Richard Henderson, 2021/02/05
- [PULL 17/46] tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}, Richard Henderson, 2021/02/05
- [PULL 18/46] tcg/tci: Merge INDEX_op_st8_{i32,i64}, Richard Henderson, 2021/02/05
- [PULL 19/46] tcg/tci: Merge INDEX_op_st16_{i32,i64}, Richard Henderson, 2021/02/05
- [PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64}, Richard Henderson, 2021/02/05
- [PULL 20/46] tcg/tci: Move stack bounds check to compile-time, Richard Henderson, 2021/02/05
- [PULL 22/46] tcg/tci: Use g_assert_not_reached, Richard Henderson, 2021/02/05
- [PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*, Richard Henderson, 2021/02/05
- [PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16,
Richard Henderson <=
- [PULL 28/46] tcg/tci: Remove TCG_CONST, Richard Henderson, 2021/02/05
- [PULL 25/46] tcg/tci: Remove TODO as unused, Richard Henderson, 2021/02/05
- [PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops, Richard Henderson, 2021/02/05
- [PULL 29/46] cpu: Introduce TCGCpuOperations struct, Richard Henderson, 2021/02/05
- [PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage, Richard Henderson, 2021/02/05
- [PULL 24/46] tcg/tci: Implement 64-bit division, Richard Henderson, 2021/02/05
- [PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG, Richard Henderson, 2021/02/05
- [PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn, Richard Henderson, 2021/02/05
- [PULL 33/46] cpu: Move cpu_exec_* to tcg_ops, Richard Henderson, 2021/02/05
- [PULL 34/46] cpu: Move tlb_fill to tcg_ops, Richard Henderson, 2021/02/05