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[PATCH v3 19/70] tcg/tci: Split out tci_args_rr
From: |
Richard Henderson |
Subject: |
[PATCH v3 19/70] tcg/tci: Split out tci_args_rr |
Date: |
Sun, 7 Feb 2021 18:37:01 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 67 +++++++++++++++++++++++++------------------------------
1 file changed, 31 insertions(+), 36 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index be298ae39d..0bc5294e8b 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -184,6 +184,13 @@ static tcg_target_ulong tci_read_label(const uint8_t
**tb_ptr)
* s = signed ldst offset
*/
+static void tci_args_rr(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+}
+
static void tci_args_rrs(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, int32_t *i2)
{
@@ -439,9 +446,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
break;
#endif
CASE_32_64(mov)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = regs[r1];
break;
case INDEX_op_tci_movi_i32:
t0 = *tb_ptr++;
@@ -652,58 +658,50 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int8_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (int8_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
CASE_32_64(ext16s)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int16_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (int16_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
CASE_32_64(ext8u)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint8_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (uint8_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
CASE_32_64(ext16u)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint16_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (uint16_t)regs[r1];
break;
#endif
#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
CASE_32_64(bswap16)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, bswap16(t1));
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = bswap16(regs[r1]);
break;
#endif
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
CASE_32_64(bswap32)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, bswap32(t1));
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = bswap32(regs[r1]);
break;
#endif
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
CASE_32_64(not)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, ~t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = ~regs[r1];
break;
#endif
#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
CASE_32_64(neg)
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, -t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = -regs[r1];
break;
#endif
#if TCG_TARGET_REG_BITS == 64
@@ -816,21 +814,18 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
break;
case INDEX_op_ext32s_i64:
case INDEX_op_ext_i32_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (int32_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (int32_t)regs[r1];
break;
case INDEX_op_ext32u_i64:
case INDEX_op_extu_i32_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, (uint32_t)t1);
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = (uint32_t)regs[r1];
break;
#if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64:
- t0 = *tb_ptr++;
- t1 = tci_read_rval(regs, &tb_ptr);
- tci_write_reg(regs, t0, bswap64(t1));
+ tci_args_rr(&tb_ptr, &r0, &r1);
+ regs[r0] = bswap64(regs[r1]);
break;
#endif
#endif /* TCG_TARGET_REG_BITS == 64 */
--
2.25.1
- [PATCH v3 08/70] tcg/tci: Remove tci_read_r16s, (continued)
- [PATCH v3 08/70] tcg/tci: Remove tci_read_r16s, Richard Henderson, 2021/02/07
- [PATCH v3 09/70] tcg/tci: Remove tci_read_r32, Richard Henderson, 2021/02/07
- [PATCH v3 13/70] tcg/tci: Merge extension operations, Richard Henderson, 2021/02/07
- [PATCH v3 14/70] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64, Richard Henderson, 2021/02/07
- [PATCH v3 10/70] tcg/tci: Remove tci_read_r32s, Richard Henderson, 2021/02/07
- [PATCH v3 11/70] tcg/tci: Reduce use of tci_read_r64, Richard Henderson, 2021/02/07
- [PATCH v3 12/70] tcg/tci: Merge basic arithmetic operations, Richard Henderson, 2021/02/07
- [PATCH v3 16/70] tcg/tci: Merge mov, not and neg operations, Richard Henderson, 2021/02/07
- [PATCH v3 18/70] tcg/tci: Split out tci_args_rrs, Richard Henderson, 2021/02/07
- [PATCH v3 15/70] tcg/tci: Merge bswap operations, Richard Henderson, 2021/02/07
- [PATCH v3 19/70] tcg/tci: Split out tci_args_rr,
Richard Henderson <=
- [PATCH v3 20/70] tcg/tci: Split out tci_args_rrr, Richard Henderson, 2021/02/07
- [PATCH v3 21/70] tcg/tci: Split out tci_args_rrrc, Richard Henderson, 2021/02/07
- [PATCH v3 17/70] tcg/tci: Rename tci_read_r to tci_read_rval, Richard Henderson, 2021/02/07
- [PATCH v3 22/70] tcg/tci: Split out tci_args_l, Richard Henderson, 2021/02/07
- [PATCH v3 24/70] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl, Richard Henderson, 2021/02/07
- [PATCH v3 26/70] tcg/tci: Reuse tci_args_l for calls., Richard Henderson, 2021/02/07
- [PATCH v3 23/70] tcg/tci: Split out tci_args_rrrrrc, Richard Henderson, 2021/02/07
- [PATCH v3 28/70] tcg/tci: Reuse tci_args_l for goto_tb, Richard Henderson, 2021/02/07
- [PATCH v3 31/70] tcg/tci: Clean up deposit operations, Richard Henderson, 2021/02/07
- [PATCH v3 27/70] tcg/tci: Reuse tci_args_l for exit_tb, Richard Henderson, 2021/02/07