[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 3/4] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for
From: |
Rebecca Cran |
Subject: |
[PATCH v5 3/4] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU |
Date: |
Sun, 7 Feb 2021 23:56:59 -0700 |
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu64.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 10c51181767d..c255f1bcc393 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
cpu->isar.id_aa64pfr0 = t;
t = cpu->isar.id_aa64pfr1;
@@ -718,6 +719,10 @@ static void aarch64_max_initfn(Object *obj)
u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
cpu->isar.id_isar6 = u;
+ u = cpu->isar.id_pfr0;
+ u = FIELD_DP32(u, ID_PFR0, DIT, 1);
+ cpu->isar.id_pfr0 = u;
+
u = cpu->isar.id_mmfr3;
u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
cpu->isar.id_mmfr3 = u;
--
2.26.2
- [PATCH v5 0/4] target/arm: Add support for FEAT_DIT, Data Independent Timing, Rebecca Cran, 2021/02/08
- [PATCH v5 2/4] target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate, Rebecca Cran, 2021/02/08
- [PATCH v5 1/4] target/arm: Add support for FEAT_DIT, Data Independent Timing, Rebecca Cran, 2021/02/08
- [PATCH v5 4/4] target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU, Rebecca Cran, 2021/02/08
- [PATCH v5 3/4] target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU,
Rebecca Cran <=
- Re: [PATCH v5 0/4] target/arm: Add support for FEAT_DIT, Data Independent Timing, Peter Maydell, 2021/02/09