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[PULL 38/46] pci-host: designware: add pcie-msi read method
From: |
Paolo Bonzini |
Subject: |
[PULL 38/46] pci-host: designware: add pcie-msi read method |
Date: |
Mon, 8 Feb 2021 19:23:23 +0100 |
From: Prasad J Pandit <pjp@fedoraproject.org>
Add pcie-msi mmio read method to avoid NULL pointer dereference
issue.
Reported-by: Lei Sun <slei.casper@gmail.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org>
Message-Id: <20200811114133.672647-3-ppandit@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
hw/pci-host/designware.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index f9fb97a3e3..bde3a343a2 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
+#include "qemu/log.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_host.h"
@@ -63,6 +64,23 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root)
return DESIGNWARE_PCIE_HOST(bus->parent);
}
+static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ /*
+ * Attempts to read from the MSI address are undefined in
+ * the PCI specifications. For this hardware, the datasheet
+ * specifies that a read from the magic address is simply not
+ * intercepted by the MSI controller, and will go out to the
+ * AHB/AXI bus like any other PCI-device-initiated DMA read.
+ * This is not trivial to implement in QEMU, so since
+ * well-behaved guests won't ever ask a PCI device to DMA from
+ * this address we just log the missing functionality.
+ */
+ qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
+ return 0;
+}
+
static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
uint64_t val, unsigned len)
{
@@ -77,6 +95,7 @@ static void designware_pcie_root_msi_write(void *opaque,
hwaddr addr,
}
static const MemoryRegionOps designware_pci_host_msi_ops = {
+ .read = designware_pcie_root_msi_read,
.write = designware_pcie_root_msi_write,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
--
2.29.2
- [PULL 37/46] hw/pci-host: add pci-intack write method, (continued)
- [PULL 37/46] hw/pci-host: add pci-intack write method, Paolo Bonzini, 2021/02/08
- [PULL 43/46] tz-ppc: add dummy read/write methods, Paolo Bonzini, 2021/02/08
- [PULL 42/46] spapr_pci: add spapr msi read method, Paolo Bonzini, 2021/02/08
- [PULL 31/46] qapi/meson: Restrict UI module to system emulation and tools, Paolo Bonzini, 2021/02/08
- [PULL 26/46] meson: Restrict some trace event directories to user/system emulation, Paolo Bonzini, 2021/02/08
- [PULL 30/46] qapi/meson: Restrict system-mode specific modules, Paolo Bonzini, 2021/02/08
- [PULL 32/46] accel/kvm/kvm-all: Fix wrong return code handling in dirty log code, Paolo Bonzini, 2021/02/08
- [PULL 33/46] replay: fix replay of the interrupts, Paolo Bonzini, 2021/02/08
- [PULL 36/46] cpu-throttle: Remove timer_mod() from cpu_throttle_set(), Paolo Bonzini, 2021/02/08
- [PULL 34/46] pc-bios/descriptors: fix paths in json files, Paolo Bonzini, 2021/02/08
- [PULL 38/46] pci-host: designware: add pcie-msi read method,
Paolo Bonzini <=
- [PULL 39/46] vfio: add quirk device write method, Paolo Bonzini, 2021/02/08
- [PULL 41/46] nvram: add nrf51_soc flash read method, Paolo Bonzini, 2021/02/08
- [PULL 44/46] imx7-ccm: add digprog mmio write method, Paolo Bonzini, 2021/02/08
- [PULL 40/46] prep: add ppc-parity write method, Paolo Bonzini, 2021/02/08
- [PULL 46/46] target/i386: Expose VMX entry/exit load pkrs control bits, Paolo Bonzini, 2021/02/08
- [PULL 45/46] target/i386: Add support for save/load IA32_PKRS MSR, Paolo Bonzini, 2021/02/08
- Re: [PULL 00/46] Misc patches for 2021-02-08, Peter Maydell, 2021/02/09