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[PULL hvf 4/5] target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT
From: |
Roman Bolshakov |
Subject: |
[PULL hvf 4/5] target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT |
Date: |
Tue, 9 Feb 2021 16:57:21 +0300 |
From: Vladislav Yaroshchuk <yaroshchuk2000@gmail.com>
Some guests (ex. Darwin-XNU) can attemp to read this MSR to retrieve and
validate CPU topology comparing it to ACPI MADT content
MSR description from Intel Manual:
35H: MSR_CORE_THREAD_COUNT: Configured State of Enabled Processor Core
Count and Logical Processor Count
Bits 15:0 THREAD_COUNT The number of logical processors that are
currently enabled in the physical package
Bits 31:16 Core_COUNT The number of processor cores that are currently
enabled in the physical package
Bits 63:32 Reserved
Signed-off-by: Vladislav Yaroshchuk <yaroshchuk2000@gmail.com>
Message-Id: <20210113205323.33310-1-yaroshchuk2000@gmail.com>
[RB: reordered MSR definition and dropped u suffix from shift offset]
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
---
target/i386/cpu.h | 1 +
target/i386/hvf/x86_emu.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d23a5b340a..e2fe0689cc 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -366,6 +366,7 @@ typedef enum X86Seg {
#define MSR_IA32_SMBASE 0x9e
#define MSR_SMI_COUNT 0x34
+#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_MTRRcap 0xfe
#define MSR_MTRRcap_VCNT 8
#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index da570e352b..e52c39ddb1 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -668,6 +668,7 @@ void simulate_rdmsr(struct CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
+ CPUState *cs = env_cpu(env);
uint32_t msr = ECX(env);
uint64_t val = 0;
@@ -745,6 +746,10 @@ void simulate_rdmsr(struct CPUState *cpu)
case MSR_MTRRdefType:
val = env->mtrr_deftype;
break;
+ case MSR_CORE_THREAD_COUNT:
+ val = cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0 */
+ val |= ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..16 */
+ break;
default:
/* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
val = 0;
--
2.30.0
- [PULL hvf 0/5] HVF updates for 2021-02-09, Roman Bolshakov, 2021/02/09
- [PULL hvf 1/5] hvf: Guard xgetbv call, Roman Bolshakov, 2021/02/09
- [PULL hvf 3/5] hvf: x86: Remove unused definitions, Roman Bolshakov, 2021/02/09
- [PULL hvf 2/5] target/i386/hvf: add vmware-cpuid-freq cpu feature, Roman Bolshakov, 2021/02/09
- [PULL hvf 4/5] target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT,
Roman Bolshakov <=
- [PULL hvf 5/5] hvf: Fetch cr4 before evaluating CPUID(1), Roman Bolshakov, 2021/02/09
- Re: [PULL hvf 0/5] HVF updates for 2021-02-09, Paolo Bonzini, 2021/02/09