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[PULL 38/45] target/arm: Add allocation tag storage for user mode
From: |
Peter Maydell |
Subject: |
[PULL 38/45] target/arm: Add allocation tag storage for user mode |
Date: |
Thu, 11 Feb 2021 12:58:53 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Use the now-saved PAGE_ANON and PAGE_MTE bits,
and the per-page saved data.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210210000223.884088-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/mte_helper.c | 29 +++++++++++++++++++++++++++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index d55f8d1e1ed..1c569336eae 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -78,8 +78,33 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int
ptr_mmu_idx,
int tag_size, uintptr_t ra)
{
#ifdef CONFIG_USER_ONLY
- /* Tag storage not implemented. */
- return NULL;
+ uint64_t clean_ptr = useronly_clean_ptr(ptr);
+ int flags = page_get_flags(clean_ptr);
+ uint8_t *tags;
+ uintptr_t index;
+
+ if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) {
+ /* SIGSEGV */
+ arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access,
+ ptr_mmu_idx, false, ra);
+ g_assert_not_reached();
+ }
+
+ /* Require both MAP_ANON and PROT_MTE for the page. */
+ if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) {
+ return NULL;
+ }
+
+ tags = page_get_target_data(clean_ptr);
+ if (tags == NULL) {
+ size_t alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1);
+ tags = page_alloc_target_data(clean_ptr, alloc_size);
+ assert(tags != NULL);
+ }
+
+ index = extract32(ptr, LOG2_TAG_GRANULE + 1,
+ TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1);
+ return tags + index;
#else
uintptr_t index;
CPUIOTLBEntry *iotlbentry;
--
2.20.1
- [PULL 27/45] linux-user: Fix types in uaccess.c, (continued)
- [PULL 27/45] linux-user: Fix types in uaccess.c, Peter Maydell, 2021/02/11
- [PULL 30/45] target/arm: Improve gen_top_byte_ignore, Peter Maydell, 2021/02/11
- [PULL 32/45] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG, Peter Maydell, 2021/02/11
- [PULL 33/45] linux-user/aarch64: Implement PROT_MTE, Peter Maydell, 2021/02/11
- [PULL 34/45] target/arm: Split out syndrome.h from internals.h, Peter Maydell, 2021/02/11
- [PULL 36/45] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault, Peter Maydell, 2021/02/11
- [PULL 43/45] tests/qtests: Add npcm7xx emc model test, Peter Maydell, 2021/02/11
- [PULL 41/45] hw/net: Add npcm7xx emc model, Peter Maydell, 2021/02/11
- [PULL 37/45] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error, Peter Maydell, 2021/02/11
- [PULL 44/45] hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2, Peter Maydell, 2021/02/11
- [PULL 38/45] target/arm: Add allocation tag storage for user mode,
Peter Maydell <=
- [PULL 40/45] tests/tcg/aarch64: Add mte smoke tests, Peter Maydell, 2021/02/11
- [PULL 42/45] hw/arm: Add npcm7xx emc model, Peter Maydell, 2021/02/11
- [PULL 45/45] target/arm: Correctly initialize MDCR_EL2.HPMN, Peter Maydell, 2021/02/11
- Re: [PULL 00/45] target-arm queue, no-reply, 2021/02/11