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Re: [PATCH v2 17/21] accel/tcg: cache single instruction TB on pending r

From: Alex Bennée
Subject: Re: [PATCH v2 17/21] accel/tcg: cache single instruction TB on pending replay exception
Date: Thu, 11 Feb 2021 20:00:40 +0000
User-agent: mu4e 1.5.8; emacs 28.0.50

Richard Henderson <richard.henderson@linaro.org> writes:

> On 2/10/21 2:10 PM, Alex Bennée wrote:
>> Again there is no reason to jump through the nocache hoops to execute
>> a single instruction block. We do have to add an additional wrinkle to
>> the cpu_handle_interrupt case to ensure we let through a TB where we
>> have specifically disabled icount for the block.
> Can you say more about this?  Because...
>>      if (unlikely(qatomic_read(&cpu->exit_request))
>>          || (icount_enabled()
>> +            && (cpu->cflags_next_tb == -1 || cpu->cflags_next_tb & 
>>              && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) 
>> {
> ... this does not appear to match.  You're checking that icount has been
> explicitly *enabled*?

If icount has been enabled and we are using the default cflags or
enabled and we have the explicit CF_ICOUNT. The replay exception leg
explicitly disables icount because otherwise we'd never actually execute
the block because we have a budget of 0 cycles left. Previously we ran
that block at the exception handling point - now we fall through and
have to make sure we don't trigger an IRQ.

> Or am I reading the logic backward and only if icount is
> enabled will we take EXCP_INTERRUPT?

Or I guess we have an exit_request which hasn't been handled yet but
there is no EXCP_ pending.

> r~

Alex Bennée

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