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[PATCH 01/38] target/riscv: implementation-defined constant parameters
From: |
LIU Zhiwei |
Subject: |
[PATCH 01/38] target/riscv: implementation-defined constant parameters |
Date: |
Fri, 12 Feb 2021 23:02:19 +0800 |
ext_p64 is whether to support Zp64 extension in RV32, default value is true.
pext_ver is the packed specification version, default value is v0.9.2.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 29 +++++++++++++++++++++++++++++
target/riscv/cpu.h | 6 ++++++
target/riscv/translate.c | 2 ++
3 files changed, 37 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16f1a34238..1b99f629ec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -132,6 +132,11 @@ static void set_vext_version(CPURISCVState *env, int
vext_ver)
env->vext_ver = vext_ver;
}
+static void set_pext_version(CPURISCVState *env, int pext_ver)
+{
+ env->pext_ver = pext_ver;
+}
+
static void set_feature(CPURISCVState *env, int feature)
{
env->features |= (1ULL << feature);
@@ -380,6 +385,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
int vext_version = VEXT_VERSION_0_07_1;
+ int pext_version = PEXT_VERSION_0_09_2;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -404,6 +410,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
set_priv_version(env, priv_version);
set_vext_version(env, vext_version);
+ set_pext_version(env, pext_version);
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
@@ -511,6 +518,28 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_vext_version(env, vext_version);
}
+ if (cpu->cfg.ext_p) {
+ target_misa |= RVP;
+ if (cpu->cfg.pext_spec) {
+ if (!g_strcmp0(cpu->cfg.pext_spec, "v0.9.2")) {
+ pext_version = PEXT_VERSION_0_09_2;
+ } else {
+ error_setg(errp,
+ "Unsupported packed spec version '%s'",
+ cpu->cfg.pext_spec);
+ return;
+ }
+ } else {
+ qemu_log("packed verison is not specified, "
+ "use the default value v0.9.2\n");
+ }
+ if (!cpu->cfg.ext_p64 && env->misa == RV64) {
+ error_setg(errp, "For RV64, the Zp64 instructions will be "
+ "included in the baseline P extension.");
+ return;
+ }
+ set_pext_version(env, pext_version);
+ }
set_misa(env, target_misa);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb..f458722646 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -68,6 +68,7 @@
#define RVF RV('F')
#define RVD RV('D')
#define RVV RV('V')
+#define RVP RV('P')
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
@@ -87,6 +88,7 @@ enum {
#define PRIV_VERSION_1_11_0 0x00011100
#define VEXT_VERSION_0_07_1 0x00000701
+#define PEXT_VERSION_0_09_2 0x00000902
enum {
TRANSLATE_SUCCESS,
@@ -134,6 +136,7 @@ struct CPURISCVState {
target_ulong priv_ver;
target_ulong vext_ver;
+ target_ulong pext_ver;
target_ulong misa;
target_ulong misa_mask;
@@ -288,13 +291,16 @@ struct RISCVCPU {
bool ext_u;
bool ext_h;
bool ext_v;
+ bool ext_p;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_p64;
char *priv_spec;
char *user_spec;
char *vext_spec;
+ char *pext_spec;
uint16_t vlen;
uint16_t elen;
bool mmu;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0f28b5f41e..eb810efec6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -56,6 +56,7 @@ typedef struct DisasContext {
to reset this known value. */
int frm;
bool ext_ifencei;
+ bool ext_p64;
bool hlsx;
/* vector extension */
bool vill;
@@ -824,6 +825,7 @@ static void riscv_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
+ ctx->ext_p64 = cpu->cfg.ext_p64;
ctx->cs = cs;
}
--
2.17.1
- [PATCH 02/38] target/riscv: Hoist vector functions, (continued)
- [PATCH 02/38] target/riscv: Hoist vector functions, LIU Zhiwei, 2021/02/12
- [PATCH 03/38] target/riscv: Fixup saturate subtract function, LIU Zhiwei, 2021/02/12
- [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction, LIU Zhiwei, 2021/02/12
- [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 09/38] target/riscv: SIMD 8-bit Compare Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 11/38] target/riscv: SIMD 8-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 01/38] target/riscv: implementation-defined constant parameters,
LIU Zhiwei <=
- [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 15/38] target/riscv: 16-bit Packing Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions, LIU Zhiwei, 2021/02/12