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[PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
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From: |
LIU Zhiwei |
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Subject: |
[PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions |
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Date: |
Fri, 12 Feb 2021 23:02:54 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 2 ++
target/riscv/insn32-64.decode | 2 ++
target/riscv/insn_trans/trans_rvp.c.inc | 3 +++
target/riscv/packed_helper.c | 13 +++++++++++++
4 files changed, 20 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 85290a2b05..d3dd1fb248 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1469,4 +1469,6 @@ DEF_HELPER_4(kmsxda32, tl, env, tl, tl, tl)
DEF_HELPER_3(smds32, tl, env, tl, tl)
DEF_HELPER_3(smdrs32, tl, env, tl, tl)
DEF_HELPER_3(smxds32, tl, env, tl, tl)
+
+DEF_HELPER_3(sraiw_u, tl, env, tl, tl)
#endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index ccdd965963..32066d3ac2 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -164,3 +164,5 @@ kmsxda32 0100111 ..... ..... 010 ..... 1111111 @r
smds32 0101100 ..... ..... 010 ..... 1111111 @r
smdrs32 0110100 ..... ..... 010 ..... 1111111 @r
smxds32 0111100 ..... ..... 010 ..... 1111111 @r
+
+sraiw_u 0011010 ..... ..... 001 ..... 1111111 @sh5
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index d2000bcfb5..57827d2e15 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1212,4 +1212,7 @@ GEN_RVP_R_ACC_OOL(kmsxda32);
GEN_RVP_R_OOL(smds32);
GEN_RVP_R_OOL(smdrs32);
GEN_RVP_R_OOL(smxds32);
+
+/* (RV64 Only) Non-SIMD 32-bit Shift Instructions */
+GEN_RVP_SHIFTI(sraiw_u, sraiw_u, NULL);
#endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index bd24d5145a..69a7788e99 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3805,4 +3805,17 @@ static inline void do_smxds32(CPURISCVState *env, void
*vd, void *va,
}
RVPR(smxds32, 1, sizeof(target_ulong));
+
+/* (RV64 Only) Non-SIMD 32-bit Shift Instructions */
+static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va;
+ uint8_t shift = *(uint8_t *)vb;
+
+ *d = vssra32(env, 0, a[H4(i)], shift);
+}
+
+RVPR(sraiw_u, 1, sizeof(target_ulong));
#endif
--
2.17.1
- [PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions, (continued)
- [PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 27/38] target/riscv: 32-bit Computation Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 33/38] target/riscv: RV64 Only 32-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions,
LIU Zhiwei <=
- [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 38/38] target/riscv: configure and turn on packed extension from command line, LIU Zhiwei, 2021/02/12