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Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructio
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions |
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Date: |
Fri, 12 Feb 2021 11:02:16 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 2/12/21 7:02 AM, LIU Zhiwei wrote:
> +static void tcg_gen_simd_add16(TCGv d, TCGv a, TCGv b)
> +{
> + TCGv t1 = tcg_temp_new();
> + TCGv t2 = tcg_temp_new();
> +
> + tcg_gen_andi_tl(t1, a, ~0xffff);
> + tcg_gen_add_tl(t2, a, b);
> + tcg_gen_add_tl(t1, t1, b);
> + tcg_gen_deposit_tl(d, t1, t2, 0, 16);
> +
> + tcg_temp_free(t1);
> + tcg_temp_free(t2);
> +}
I will note that there are some helper functions, e.g. tcg_gen_vec_add16_i64
(see the end of include/tcg/tcg-op-gvec.h), but those are explicitly i64, and
you'll still need these for rv32.
r~
[PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction, LIU Zhiwei, 2021/02/12
[PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions, LIU Zhiwei, 2021/02/12
[PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions, LIU Zhiwei, 2021/02/12
[PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions, LIU Zhiwei, 2021/02/12
[PATCH 09/38] target/riscv: SIMD 8-bit Compare Instructions, LIU Zhiwei, 2021/02/12
[PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
[PATCH 11/38] target/riscv: SIMD 8-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
[PATCH 01/38] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2021/02/12