[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public
|
From: |
Philippe Mathieu-Daudé |
|
Subject: |
[RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public |
|
Date: |
Sun, 14 Feb 2021 18:58:33 +0100 |
We will access the cpu_HI/LO registers outside of translate.c.
Make them publicly accessible.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 1 +
target/mips/translate.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index f47b5f2c8d0..2a1d8f570bb 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -145,6 +145,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int
sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
extern TCGv_i64 fpu_f64[32];
extern TCGv bcond;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a5cf1742a8b..be40f79229f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2179,7 +2179,7 @@ enum {
/* global register indices */
TCGv cpu_gpr[32], cpu_PC;
-static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
+TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
--
2.26.2
- [RFC PATCH 00/42] target/mips: Reintroduce the R5900 CPU (with more testing), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 01/42] linux-user/mips64: Restore setup_frame() for o32 ABI, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 02/42] linux-user/mips64: Support o32 ABI syscalls, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public,
Philippe Mathieu-Daudé <=
- [RFC PATCH 04/42] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 05/42] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers, Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79(), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/02/14