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Re: Fill tlb for data and io address

From: Peter Maydell
Subject: Re: Fill tlb for data and io address
Date: Tue, 16 Feb 2021 14:41:31 +0000

On Tue, 16 Feb 2021 at 14:39, 沈梦姣 <shen.mengjiao3@icloud.com> wrote:
> > 在 2021年2月16日,下午7:48,Peter Maydell <peter.maydell@linaro.org> 写道:
> >
> > On Tue, 16 Feb 2021 at 11:28, 沈梦姣 <shen.mengjiao3@icloud.com> wrote:
> >> Look at the store/load helper, it will use the tlb entry to do the address 
> >> translation(from guest virtual address to host virtual address) but where 
> >> the tlb is filled for the data ram and io address, I know where the code 
> >> ram is filled(tb_find->tb_lookup__cpu_state...)
> >
> > The common QEMU code calls the target
> Thanks Peter. But what’s the common code? I mean in which case the tlb_fill 
> will be triggered, the generated code will trigger or something else? Thanks 
> in advance.

"git grep tlb_fill accel/tcg" will tell you the call sites.
Basically if the guest code tries to access an address and
we don't already have that in the QEMU TLB, then we call

> > CPU tlb_fill function, which tries
> > to translate the guest virtual address to a physical address (usually by
> > walking the guest page tables). If it succeeds then will update the QEMU
> > TLB by calling either tlb_set_page() or tlb_set_page_with_attrs().
> > If it
> > fails then it arranges to deliver a suitable exception to the guest.
> This should be page fault, guest code will update page table, am I right? 
> Thanks

It depends on the guest architecture, but yes, that's the usual thing.

-- PMM

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