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[PULL 27/40] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check
From: |
Peter Maydell |
Subject: |
[PULL 27/40] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault |
Date: |
Tue, 16 Feb 2021 16:16:45 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210212184902.1251044-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/aarch64/target_signal.h | 2 ++
linux-user/aarch64/cpu_loop.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/linux-user/aarch64/target_signal.h
b/linux-user/aarch64/target_signal.h
index ddd73169f0f..777fb667fea 100644
--- a/linux-user/aarch64/target_signal.h
+++ b/linux-user/aarch64/target_signal.h
@@ -21,5 +21,7 @@ typedef struct target_sigaltstack {
#include "../generic/signal.h"
+#define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */
+
#define TARGET_ARCH_HAS_SETUP_FRAME
#endif /* AARCH64_TARGET_SIGNAL_H */
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 4e43906e66a..b6a2e65593f 100644
--- a/linux-user/aarch64/cpu_loop.c
+++ b/linux-user/aarch64/cpu_loop.c
@@ -134,6 +134,9 @@ void cpu_loop(CPUARMState *env)
case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
info.si_code = TARGET_SEGV_ACCERR;
break;
+ case 0x11: /* Synchronous Tag Check Fault */
+ info.si_code = TARGET_SEGV_MTESERR;
+ break;
default:
g_assert_not_reached();
}
--
2.20.1
- [PULL 23/40] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG, (continued)
- [PULL 23/40] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG, Peter Maydell, 2021/02/16
- [PULL 26/40] linux-user/aarch64: Pass syndrome to EXC_*_ABORT, Peter Maydell, 2021/02/16
- [PULL 30/40] target/arm: Enable MTE for user-only, Peter Maydell, 2021/02/16
- [PULL 28/40] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error, Peter Maydell, 2021/02/16
- [PULL 34/40] hw/arm: Add I2C sensors and EEPROM for GSJ machine, Peter Maydell, 2021/02/16
- [PULL 32/40] hw/i2c: Implement NPCM7XX SMBus Module Single Mode, Peter Maydell, 2021/02/16
- [PULL 29/40] target/arm: Add allocation tag storage for user mode, Peter Maydell, 2021/02/16
- [PULL 35/40] hw/i2c: Add a QTest for NPCM7XX SMBus Device, Peter Maydell, 2021/02/16
- [PULL 25/40] target/arm: Split out syndrome.h from internals.h, Peter Maydell, 2021/02/16
- [PULL 31/40] tests/tcg/aarch64: Add mte smoke tests, Peter Maydell, 2021/02/16
- [PULL 27/40] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault,
Peter Maydell <=
- [PULL 39/40] hw/arm: Add npcm7xx emc model, Peter Maydell, 2021/02/16
- [PULL 33/40] hw/arm: Add I2C sensors for NPCM750 eval board, Peter Maydell, 2021/02/16
- [PULL 36/40] hw/i2c: Implement NPCM7XX SMBus Module FIFO Mode, Peter Maydell, 2021/02/16
- [PULL 37/40] MAINTAINERS: add myself maintainer for the clock framework, Peter Maydell, 2021/02/16
- [PULL 40/40] tests/qtests: Add npcm7xx emc model test, Peter Maydell, 2021/02/16
- [PULL 38/40] hw/net: Add npcm7xx emc model, Peter Maydell, 2021/02/16
- Re: [PULL 00/40] target-arm queue, no-reply, 2021/02/16