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[PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl
From: |
Richard Henderson |
Subject: |
[PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl |
Date: |
Wed, 17 Feb 2021 12:19:49 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 52 ++++++++++++++++++++++++++++++++--------------------
1 file changed, 32 insertions(+), 20 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 558d03fd1b..c8df45ce28 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -212,6 +212,15 @@ static void tci_args_rrs(const uint8_t **tb_ptr,
*i2 = tci_read_s32(tb_ptr);
}
+static void tci_args_rrcl(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *c2 = tci_read_b(tb_ptr);
+ *l3 = (void *)tci_read_label(tb_ptr);
+}
+
static void tci_args_rrrc(const uint8_t **tb_ptr,
TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
{
@@ -222,6 +231,17 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
}
#if TCG_TARGET_REG_BITS == 32
+static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+ *c4 = tci_read_b(tb_ptr);
+ *l5 = (void *)tci_read_label(tb_ptr);
+}
+
static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
{
@@ -388,7 +408,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tcg_target_ulong t0;
tcg_target_ulong t1;
tcg_target_ulong t2;
- tcg_target_ulong label;
TCGCond condition;
target_ulong taddr;
uint8_t tmp8;
@@ -397,7 +416,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
TCGReg r3, r4;
- uint64_t v64, T1, T2;
+ uint64_t T1, T2;
#endif
TCGMemOpIdx oi;
int32_t ofs;
@@ -594,13 +613,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
break;
#endif
case INDEX_op_brcond_i32:
- t0 = tci_read_rval(regs, &tb_ptr);
- t1 = tci_read_rval(regs, &tb_ptr);
- condition = *tb_ptr++;
- label = tci_read_label(&tb_ptr);
- if (tci_compare32(t0, t1, condition)) {
+ tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
+ if (tci_compare32(regs[r0], regs[r1], condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
- tb_ptr = (uint8_t *)label;
+ tb_ptr = ptr;
continue;
}
break;
@@ -620,13 +636,12 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tci_write_reg64(regs, t1, t0, tmp64);
break;
case INDEX_op_brcond2_i32:
- tmp64 = tci_read_r64(regs, &tb_ptr);
- v64 = tci_read_r64(regs, &tb_ptr);
- condition = *tb_ptr++;
- label = tci_read_label(&tb_ptr);
- if (tci_compare64(tmp64, v64, condition)) {
+ tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr);
+ T1 = tci_uint64(regs[r1], regs[r0]);
+ T2 = tci_uint64(regs[r3], regs[r2]);
+ if (tci_compare64(T1, T2, condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
- tb_ptr = (uint8_t *)label;
+ tb_ptr = ptr;
continue;
}
break;
@@ -766,13 +781,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
break;
#endif
case INDEX_op_brcond_i64:
- t0 = tci_read_rval(regs, &tb_ptr);
- t1 = tci_read_rval(regs, &tb_ptr);
- condition = *tb_ptr++;
- label = tci_read_label(&tb_ptr);
- if (tci_compare64(t0, t1, condition)) {
+ tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
+ if (tci_compare64(regs[r0], regs[r1], condition)) {
tci_assert(tb_ptr == old_code_ptr + op_size);
- tb_ptr = (uint8_t *)label;
+ tb_ptr = ptr;
continue;
}
break;
--
2.25.1
- [PATCH v4 13/71] tcg/tci: Merge extension operations, (continued)
- [PATCH v4 13/71] tcg/tci: Merge extension operations, Richard Henderson, 2021/02/17
- [PATCH v4 14/71] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64, Richard Henderson, 2021/02/17
- [PATCH v4 15/71] tcg/tci: Merge bswap operations, Richard Henderson, 2021/02/17
- [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations, Richard Henderson, 2021/02/17
- [PATCH v4 17/71] tcg/tci: Rename tci_read_r to tci_read_rval, Richard Henderson, 2021/02/17
- [PATCH v4 18/71] tcg/tci: Split out tci_args_rrs, Richard Henderson, 2021/02/17
- [PATCH v4 19/71] tcg/tci: Split out tci_args_rr, Richard Henderson, 2021/02/17
- [PATCH v4 21/71] tcg/tci: Split out tci_args_rrrc, Richard Henderson, 2021/02/17
- [PATCH v4 20/71] tcg/tci: Split out tci_args_rrr, Richard Henderson, 2021/02/17
- [PATCH v4 22/71] tcg/tci: Split out tci_args_l, Richard Henderson, 2021/02/17
- [PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl,
Richard Henderson <=
- [PATCH v4 26/71] tcg/tci: Reuse tci_args_l for calls., Richard Henderson, 2021/02/17
- [PATCH v4 23/71] tcg/tci: Split out tci_args_rrrrrc, Richard Henderson, 2021/02/17
- [PATCH v4 25/71] tcg/tci: Split out tci_args_ri and tci_args_rI, Richard Henderson, 2021/02/17
- [PATCH v4 31/71] tcg/tci: Clean up deposit operations, Richard Henderson, 2021/02/17
- [PATCH v4 30/71] tcg/tci: Split out tci_args_rrrr, Richard Henderson, 2021/02/17
- [PATCH v4 27/71] tcg/tci: Reuse tci_args_l for exit_tb, Richard Henderson, 2021/02/17
- [PATCH v4 28/71] tcg/tci: Reuse tci_args_l for goto_tb, Richard Henderson, 2021/02/17
- [PATCH v4 32/71] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits, Richard Henderson, 2021/02/17
- [PATCH v4 33/71] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm}, Richard Henderson, 2021/02/17
- [PATCH v4 29/71] tcg/tci: Split out tci_args_rrrrrr, Richard Henderson, 2021/02/17