[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 01/19] target/riscv: Declare csr_ops[] with a known size
From: |
Alistair Francis |
Subject: |
[PULL 01/19] target/riscv: Declare csr_ops[] with a known size |
Date: |
Wed, 17 Feb 2021 17:59:16 -0800 |
From: Bin Meng <bin.meng@windriver.com>
csr_ops[] is currently declared with an unknown size in cpu.h.
Since the array size is known, let's do a complete declaration.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1611024723-14293-1-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb..419a21478c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -487,7 +487,7 @@ enum {
};
/* CSR function table */
-extern riscv_csr_operations csr_ops[];
+extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
--
2.30.0
- [PULL 00/19] riscv-to-apply queue, Alistair Francis, 2021/02/17
- [PULL 01/19] target/riscv: Declare csr_ops[] with a known size,
Alistair Francis <=
- [PULL 02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails, Alistair Francis, 2021/02/17
- [PULL 05/19] hw/block: m25p80: Add ISSI SPI flash support, Alistair Francis, 2021/02/17
- [PULL 04/19] target-riscv: support QMP dump-guest-memory, Alistair Francis, 2021/02/17
- [PULL 07/19] hw/ssi: Add SiFive SPI controller support, Alistair Francis, 2021/02/17
- [PULL 06/19] hw/block: m25p80: Add various ISSI flash information, Alistair Francis, 2021/02/17
- [PULL 03/19] roms/opensbi: Upgrade from v0.8 to v0.9, Alistair Francis, 2021/02/17
- [PULL 08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Alistair Francis, 2021/02/17
- [PULL 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Alistair Francis, 2021/02/17
- [PULL 10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value, Alistair Francis, 2021/02/17
- [PULL 11/19] docs/system: Sort targets in alphabetical order, Alistair Francis, 2021/02/17