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[PULL 11/19] docs/system: Sort targets in alphabetical order
From: |
Alistair Francis |
Subject: |
[PULL 11/19] docs/system: Sort targets in alphabetical order |
Date: |
Wed, 17 Feb 2021 17:59:26 -0800 |
From: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-8-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/targets.rst | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/docs/system/targets.rst b/docs/system/targets.rst
index 560783644d..564cea9a9b 100644
--- a/docs/system/targets.rst
+++ b/docs/system/targets.rst
@@ -7,16 +7,21 @@ various targets are mentioned in the following sections.
Contents:
+..
+ This table of contents should be kept sorted alphabetically
+ by the title text of each file, which isn't the same ordering
+ as an alphabetical sort by filename.
+
.. toctree::
- target-i386
+ target-arm
+ target-avr
+ target-m68k
+ target-mips
target-ppc
+ target-rx
+ target-s390x
target-sparc
target-sparc64
- target-mips
- target-arm
- target-m68k
+ target-i386
target-xtensa
- target-s390x
- target-rx
- target-avr
--
2.30.0
- [PULL 01/19] target/riscv: Declare csr_ops[] with a known size, (continued)
- [PULL 01/19] target/riscv: Declare csr_ops[] with a known size, Alistair Francis, 2021/02/17
- [PULL 02/19] hw/misc: sifive_u_otp: Use error_report() when block operation fails, Alistair Francis, 2021/02/17
- [PULL 05/19] hw/block: m25p80: Add ISSI SPI flash support, Alistair Francis, 2021/02/17
- [PULL 04/19] target-riscv: support QMP dump-guest-memory, Alistair Francis, 2021/02/17
- [PULL 07/19] hw/ssi: Add SiFive SPI controller support, Alistair Francis, 2021/02/17
- [PULL 06/19] hw/block: m25p80: Add various ISSI flash information, Alistair Francis, 2021/02/17
- [PULL 03/19] roms/opensbi: Upgrade from v0.8 to v0.9, Alistair Francis, 2021/02/17
- [PULL 08/19] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Alistair Francis, 2021/02/17
- [PULL 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Alistair Francis, 2021/02/17
- [PULL 10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value, Alistair Francis, 2021/02/17
- [PULL 11/19] docs/system: Sort targets in alphabetical order,
Alistair Francis <=
- [PULL 13/19] docs/system: riscv: Add documentation for sifive_u machine, Alistair Francis, 2021/02/17
- [PULL 12/19] docs/system: Add RISC-V documentation, Alistair Francis, 2021/02/17
- [PULL 14/19] goldfish_rtc: re-arm the alarm after migration, Alistair Francis, 2021/02/17
- [PULL 15/19] MAINTAINERS: Add a SiFive machine section, Alistair Francis, 2021/02/17
- [PULL 16/19] hw/riscv: Drop 'struct MemmapEntry', Alistair Francis, 2021/02/17
- [PULL 17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init(), Alistair Francis, 2021/02/17
- [PULL 18/19] hw/riscv: virt: Limit RAM size in a 32-bit system, Alistair Francis, 2021/02/17
- [PULL 19/19] hw/riscv: virt: Map high mmio for PCIe, Alistair Francis, 2021/02/17
- Re: [PULL 00/19] riscv-to-apply queue, Peter Maydell, 2021/02/18