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[PULL 19/19] hw/riscv: virt: Map high mmio for PCIe
From: |
Alistair Francis |
Subject: |
[PULL 19/19] hw/riscv: virt: Map high mmio for PCIe |
Date: |
Wed, 17 Feb 2021 17:59:34 -0800 |
From: Bin Meng <bin.meng@windriver.com>
Some peripherals require 64-bit PCI address, so let's map the high
mmio space for PCIe.
For RV32, the address is hardcoded to below 4 GiB from the highest
accessible physical address. For RV64, the base address depends on
top of RAM and is aligned to its size which is using 16 GiB for now.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210122122958.12311-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4f44509360..4ab3b35cc7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -59,6 +59,15 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_DRAM] = { 0x80000000, 0x0 },
};
+/* PCIe high mmio is fixed for RV32 */
+#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
+#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
+
+/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
+#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
+
+static MemMapEntry virt_high_pcie_memmap;
+
#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
@@ -371,7 +380,11 @@ static void create_fdt(RISCVVirtState *s, const
MemMapEntry *memmap,
2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
1, FDT_PCI_RANGE_MMIO,
2, memmap[VIRT_PCIE_MMIO].base,
- 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
+ 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
+ 1, FDT_PCI_RANGE_MMIO_64BIT,
+ 2, virt_high_pcie_memmap.base,
+ 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
+
create_pcie_irq_map(fdt, name, plic_pcie_phandle);
g_free(name);
@@ -448,12 +461,14 @@ update_bootargs:
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
hwaddr ecam_base, hwaddr ecam_size,
hwaddr mmio_base, hwaddr mmio_size,
+ hwaddr high_mmio_base,
+ hwaddr high_mmio_size,
hwaddr pio_base,
DeviceState *plic)
{
DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg;
- MemoryRegion *mmio_alias, *mmio_reg;
+ MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
qemu_irq irq;
int i;
@@ -473,6 +488,13 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion
*sys_mem,
mmio_reg, mmio_base, mmio_size);
memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
+ /* Map high MMIO space */
+ high_mmio_alias = g_new0(MemoryRegion, 1);
+ memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
+ mmio_reg, high_mmio_base, high_mmio_size);
+ memory_region_add_subregion(get_system_memory(), high_mmio_base,
+ high_mmio_alias);
+
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
for (i = 0; i < GPEX_NUM_IRQS; i++) {
@@ -601,6 +623,14 @@ static void virt_machine_init(MachineState *machine)
machine->ram_size = 10 * GiB;
error_report("Limitting RAM size to 10 GiB");
}
+
+ virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
+ virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
+ } else {
+ virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
+ virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base +
machine->ram_size;
+ virt_high_pcie_memmap.base =
+ ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
}
/* register system main memory (actual RAM) */
@@ -686,6 +716,8 @@ static void virt_machine_init(MachineState *machine)
memmap[VIRT_PCIE_ECAM].size,
memmap[VIRT_PCIE_MMIO].base,
memmap[VIRT_PCIE_MMIO].size,
+ virt_high_pcie_memmap.base,
+ virt_high_pcie_memmap.size,
memmap[VIRT_PCIE_PIO].base,
DEVICE(pcie_plic));
--
2.30.0
- [PULL 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, (continued)
- [PULL 09/19] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Alistair Francis, 2021/02/17
- [PULL 10/19] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value, Alistair Francis, 2021/02/17
- [PULL 11/19] docs/system: Sort targets in alphabetical order, Alistair Francis, 2021/02/17
- [PULL 13/19] docs/system: riscv: Add documentation for sifive_u machine, Alistair Francis, 2021/02/17
- [PULL 12/19] docs/system: Add RISC-V documentation, Alistair Francis, 2021/02/17
- [PULL 14/19] goldfish_rtc: re-arm the alarm after migration, Alistair Francis, 2021/02/17
- [PULL 15/19] MAINTAINERS: Add a SiFive machine section, Alistair Francis, 2021/02/17
- [PULL 16/19] hw/riscv: Drop 'struct MemmapEntry', Alistair Francis, 2021/02/17
- [PULL 17/19] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init(), Alistair Francis, 2021/02/17
- [PULL 18/19] hw/riscv: virt: Limit RAM size in a 32-bit system, Alistair Francis, 2021/02/17
- [PULL 19/19] hw/riscv: virt: Map high mmio for PCIe,
Alistair Francis <=
- Re: [PULL 00/19] riscv-to-apply queue, Peter Maydell, 2021/02/18
- Re: [PULL 00/19] riscv-to-apply queue, Bin Meng, 2021/02/18
- Re: [PULL 00/19] riscv-to-apply queue, Peter Maydell, 2021/02/18
- Re: [PULL 00/19] riscv-to-apply queue, Bin Meng, 2021/02/19
- Re: [PULL 00/19] riscv-to-apply queue, Philippe Mathieu-Daudé, 2021/02/19
- Re: [PULL 00/19] riscv-to-apply queue, Peter Maydell, 2021/02/19
- Re: [PULL 00/19] riscv-to-apply queue, Richard W.M. Jones, 2021/02/19