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Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructio
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions |
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Date: |
Thu, 18 Feb 2021 08:20:46 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 2/18/21 12:39 AM, LIU Zhiwei wrote:
> On 2021/2/13 2:03, Richard Henderson wrote:
>> On 2/12/21 7:02 AM, LIU Zhiwei wrote:
>>> + if (a->rd && a->rs1 && a->rs2) {
>>> +#ifdef TARGET_RISCV64
>>> + f64(vece, offsetof(CPURISCVState, gpr[a->rd]),
>>> + offsetof(CPURISCVState, gpr[a->rs1]),
>>> + offsetof(CPURISCVState, gpr[a->rs2]),
>>> + 8, 8);
>>> +#else
>> This is not legal tcg.
>>
>> You cannot reference as memory anything which has an associated
>> tcg_global_mem.
> Thanks.
>
> Do you mean referring a global TCGTemp as memory will cause not consistent
> between TCGContext::temps and
> CPUArchState field?
Yes, there is nothing that will keep them in sync.
r~
[PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction, LIU Zhiwei, 2021/02/12
[PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions, LIU Zhiwei, 2021/02/12
[PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions, LIU Zhiwei, 2021/02/12
[PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions, LIU Zhiwei, 2021/02/12
[PATCH 09/38] target/riscv: SIMD 8-bit Compare Instructions, LIU Zhiwei, 2021/02/12
[PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
[PATCH 11/38] target/riscv: SIMD 8-bit Multiply Instructions, LIU Zhiwei, 2021/02/12