[Bug 1916269] [NEW] TCG: QEMU raises exception on SSE4.2 CRC32 instruction in kernel

[Alexander Richardson]

Public bug reported:

If I run FreeBSD on QEMU 5.2 with TCG acceleration -cpu Nehalem, I get a
FPU exception when executing crc32
(https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=253617). This is not
a problem with the default CPU (or KVM) since that does not support SSE
4.2.

Attaching GDB shows this is triggered in
target/i386/tcg/translate.c:3067

    /* simple MMX/SSE operation */
    if (s->flags & HF_TS_MASK) {
        gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
        return;
    }

However, according to
https://software.intel.com/sites/default/files/m/8/b/8/D9156103.pdf,
page 61 the CRC32 instruction works no matter what the value of the TS
bit.

The code sequence in question is:
0xffffffff8105a4de <+126>:      f2 48 0f 38 f1 de       crc32q %rsi,%rbx
0xffffffff8105a4e4 <+132>:      f2 48 0f 38 f1 ca       crc32q %rdx,%rcx.

This should work even with the FPU disabled.

** Affects: qemu
     Importance: Undecided
         Status: New

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https://bugs.launchpad.net/bugs/1916269

Title:
  TCG: QEMU raises exception on SSE4.2 CRC32 instruction in kernel

Status in QEMU:
  New

Bug description:
  If I run FreeBSD on QEMU 5.2 with TCG acceleration -cpu Nehalem, I get
  a FPU exception when executing crc32
  (https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=253617). This is
  not a problem with the default CPU (or KVM) since that does not
  support SSE 4.2.

  Attaching GDB shows this is triggered in
  target/i386/tcg/translate.c:3067

      /* simple MMX/SSE operation */
      if (s->flags & HF_TS_MASK) {
          gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
          return;
      }

  However, according to
  https://software.intel.com/sites/default/files/m/8/b/8/D9156103.pdf,
  page 61 the CRC32 instruction works no matter what the value of the TS
  bit.

  The code sequence in question is:
  0xffffffff8105a4de <+126>:    f2 48 0f 38 f1 de       crc32q %rsi,%rbx
  0xffffffff8105a4e4 <+132>:    f2 48 0f 38 f1 ca       crc32q %rdx,%rcx.

  This should work even with the FPU disabled.

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