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[PULL 17/43] target/mips: Let raise_mmu_exception() take MMUAccessType a
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 17/43] target/mips: Let raise_mmu_exception() take MMUAccessType argument |
Date: |
Sun, 21 Feb 2021 15:34:06 +0100 |
Both mips_cpu_tlb_fill() and cpu_mips_translate_address() pass
MMUAccessType to raise_mmu_exception(). Let the prototype use it
as argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-11-f4bug@amsat.org>
---
target/mips/tlb_helper.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 9bb635885dd..0ad2d51b11c 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -405,12 +405,12 @@ void cpu_mips_tlb_flush(CPUMIPSState *env)
#endif /* !CONFIG_USER_ONLY */
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
- int rw, int tlb_error)
+ MMUAccessType access_type, int tlb_error)
{
CPUState *cs = env_cpu(env);
int exception = 0, error_code = 0;
- if (rw == MMU_INST_FETCH) {
+ if (access_type == MMU_INST_FETCH) {
error_code |= EXCP_INST_NOTAVAIL;
}
@@ -419,7 +419,7 @@ static void raise_mmu_exception(CPUMIPSState *env,
target_ulong address,
case TLBRET_BADADDR:
/* Reference to kernel address from user mode or supervisor mode */
/* Reference to supervisor address from user mode */
- if (rw == MMU_DATA_STORE) {
+ if (access_type == MMU_DATA_STORE) {
exception = EXCP_AdES;
} else {
exception = EXCP_AdEL;
@@ -427,7 +427,7 @@ static void raise_mmu_exception(CPUMIPSState *env,
target_ulong address,
break;
case TLBRET_NOMATCH:
/* No TLB match for a mapped address */
- if (rw == MMU_DATA_STORE) {
+ if (access_type == MMU_DATA_STORE) {
exception = EXCP_TLBS;
} else {
exception = EXCP_TLBL;
@@ -436,7 +436,7 @@ static void raise_mmu_exception(CPUMIPSState *env,
target_ulong address,
break;
case TLBRET_INVALID:
/* TLB match with no valid bit */
- if (rw == MMU_DATA_STORE) {
+ if (access_type == MMU_DATA_STORE) {
exception = EXCP_TLBS;
} else {
exception = EXCP_TLBL;
--
2.26.2
- [PULL 08/43] target/mips: fetch code with translator_ld, (continued)
- [PULL 08/43] target/mips: fetch code with translator_ld, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 04/43] hw/mips/boston: Use bl_gen_kernel_jump to generate bootloaders, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 09/43] target/mips: Remove access_type argument from map_address() handler, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 10/43] target/mips: Remove access_type argument from get_seg_physical_address, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 11/43] target/mips: Remove access_type arg from get_segctl_physical_address(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 12/43] target/mips: Remove access_type argument from get_physical_address(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 13/43] target/mips: Remove unused MMU definitions, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 14/43] target/mips: Replace magic value by MMU_DATA_LOAD definition, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 15/43] target/mips: Let do_translate_address() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 16/43] target/mips: Let cpu_mips_translate_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 17/43] target/mips: Let raise_mmu_exception() take MMUAccessType argument,
Philippe Mathieu-Daudé <=
- [PULL 18/43] target/mips: Let get_physical_address() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 19/43] target/mips: Let get_seg*_physical_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 23/43] target/mips: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 29/43] vt82c686: Reorganise code, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/21