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[PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUA
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType |
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Date: |
Sun, 21 Feb 2021 15:34:09 +0100 |
get_seg_physical_address() calls CPUMIPSTLBContext::map_address()
handlers passing a MMUAccessType type. Update the prototype
handlers to take a MMUAccessType argument, as it is stricter than
an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-14-f4bug@amsat.org>
---
target/mips/internal.h | 8 ++++----
target/mips/tlb_helper.c | 12 ++++++------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 34915c275c4..99264b8bf6a 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -111,7 +111,7 @@ struct CPUMIPSTLBContext {
uint32_t nb_tlb;
uint32_t tlb_in_use;
int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw);
+ target_ulong address, MMUAccessType access_type);
void (*helper_tlbwi)(struct CPUMIPSState *env);
void (*helper_tlbwr)(struct CPUMIPSState *env);
void (*helper_tlbp)(struct CPUMIPSState *env);
@@ -126,11 +126,11 @@ struct CPUMIPSTLBContext {
};
int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw);
+ target_ulong address, MMUAccessType access_type);
int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw);
+ target_ulong address, MMUAccessType access_type);
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw);
+ target_ulong address, MMUAccessType access_type);
void r4k_helper_tlbwi(CPUMIPSState *env);
void r4k_helper_tlbwr(CPUMIPSState *env);
void r4k_helper_tlbp(CPUMIPSState *env);
diff --git a/target/mips/tlb_helper.c b/target/mips/tlb_helper.c
index 4db8a7582d4..b48f892a513 100644
--- a/target/mips/tlb_helper.c
+++ b/target/mips/tlb_helper.c
@@ -39,7 +39,7 @@ enum {
/* no MMU emulation */
int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw)
+ target_ulong address, MMUAccessType access_type)
{
*physical = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -48,7 +48,7 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical,
int *prot,
/* fixed mapping MMU emulation */
int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw)
+ target_ulong address, MMUAccessType access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
if (!(env->CP0_Status & (1 << CP0St_ERL))) {
@@ -68,7 +68,7 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr
*physical, int *prot,
/* MIPS32/MIPS64 R4000-style MMU emulation */
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw)
+ target_ulong address, MMUAccessType access_type)
{
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
uint32_t MMID = env->CP0_MemoryMapID;
@@ -97,13 +97,13 @@ int r4k_map_address(CPUMIPSState *env, hwaddr *physical,
int *prot,
if (!(n ? tlb->V1 : tlb->V0)) {
return TLBRET_INVALID;
}
- if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
+ if (access_type == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
return TLBRET_XI;
}
- if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
+ if (access_type == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
return TLBRET_RI;
}
- if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
+ if (access_type != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
*physical = tlb->PFN[n] | (address & (mask >> 1));
*prot = PAGE_READ;
if (n ? tlb->D1 : tlb->D0) {
--
2.26.2
- [PULL 10/43] target/mips: Remove access_type argument from get_seg_physical_address, (continued)
- [PULL 10/43] target/mips: Remove access_type argument from get_seg_physical_address, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 11/43] target/mips: Remove access_type arg from get_segctl_physical_address(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 12/43] target/mips: Remove access_type argument from get_physical_address(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 13/43] target/mips: Remove unused MMU definitions, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 14/43] target/mips: Replace magic value by MMU_DATA_LOAD definition, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 15/43] target/mips: Let do_translate_address() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 16/43] target/mips: Let cpu_mips_translate_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 17/43] target/mips: Let raise_mmu_exception() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 18/43] target/mips: Let get_physical_address() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 19/43] target/mips: Let get_seg*_physical_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType,
Philippe Mathieu-Daudé <=
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 23/43] target/mips: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 29/43] vt82c686: Reorganise code, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 32/43] vt82c686: Correct vt82c686-pm I/O size, Philippe Mathieu-Daudé, 2021/02/21