[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region |
Date: |
Sun, 21 Feb 2021 15:34:20 +0100 |
From: BALATON Zoltan <balaton@eik.bme.hu>
Previously just an empty RAM region was mapped on realize, now we add
an empty io range logging access instead. I think the pm timer should
be hooked up here but not sure guests need it. PMON on fuloong2e sets
a base address but does not seem to enable region; the pegasos2
firmware pokes some regs but continues anyway so don't know if
anything would make use of these facilities. Therefore this is just a
clean up of previous state for now and not intending to fully
implement missing functionality which could be done later if some
guests need it.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu>
[PMD: Split original patch, this is part 1/4
(make 'vt82c686-pm' an I/O tracing region)]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/vt82c686.c | 26 ++++++++++++++++++++++++--
hw/isa/trace-events | 2 ++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 9c4d1530225..7e6a07fca48 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -102,6 +102,27 @@ static void pm_write_config(PCIDevice *d, uint32_t addr,
uint32_t val, int len)
}
}
+static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size)
+{
+ trace_via_pm_io_write(addr, data, size);
+}
+
+static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size)
+{
+ trace_via_pm_io_read(addr, 0, size);
+ return 0;
+}
+
+static const MemoryRegionOps pm_io_ops = {
+ .read = pm_io_read,
+ .write = pm_io_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
static void pm_update_sci(VT686PMState *s)
{
int sci_level, pmsts;
@@ -154,9 +175,10 @@ static void vt82c686b_pm_realize(PCIDevice *dev, Error
**errp)
apm_init(dev, &s->apm, NULL, s);
- memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64);
+ memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s,
+ "vt82c686-pm", 64);
+ memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io);
memory_region_set_enabled(&s->io, false);
- memory_region_add_subregion(get_system_io(), 0, &s->io);
acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
diff --git a/hw/isa/trace-events b/hw/isa/trace-events
index d267d3e6524..641d69eedf7 100644
--- a/hw/isa/trace-events
+++ b/hw/isa/trace-events
@@ -17,5 +17,7 @@ apm_io_write(uint8_t addr, uint8_t val) "write addr=0x%x
val=0x%02x"
# vt82c686.c
via_isa_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
0x%x"
via_pm_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
0x%x"
+via_pm_io_read(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
0x%x"
+via_pm_io_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len
0x%x"
via_superio_read(uint8_t addr, uint8_t val) "addr 0x%x val 0x%x"
via_superio_write(uint8_t addr, uint32_t val) "addr 0x%x val 0x%x"
--
2.26.2
- [PULL 18/43] target/mips: Let get_physical_address() take MMUAccessType argument, (continued)
- [PULL 18/43] target/mips: Let get_physical_address() take MMUAccessType argument, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 19/43] target/mips: Let get_seg*_physical_address() take MMUAccessType arg, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 20/43] target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 21/43] target/mips: Remove unused 'rw' argument from page_table_walk_refill(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 22/43] target/mips: Include missing "tcg/tcg.h" header, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 23/43] target/mips: Make cpu_HI/LO registers public, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 25/43] target/mips: Rename 128-bit upper halve GPR registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 29/43] vt82c686: Reorganise code, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 28/43] vt82c686: Move superio memory region to SuperIOConfig struct, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 24/43] target/mips: Promote 128-bit multimedia registers as global ones, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 31/43] vt82c686: Make vt82c686-pm an I/O tracing region,
Philippe Mathieu-Daudé <=
- [PULL 26/43] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 32/43] vt82c686: Correct vt82c686-pm I/O size, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 27/43] target/mips: Use GPR move functions in gen_HILO1_tx79(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 30/43] vt82c686: Fix SMBus IO base and configuration registers, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 33/43] vt82c686: Correctly reset all registers to default values on reset, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 34/43] vt82c686: Fix up power management io base and config, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 35/43] vt82c686: Set user_creatable=false for VT82C686B_PM, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 36/43] vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on it, Philippe Mathieu-Daudé, 2021/02/21
- [PULL 37/43] vt82c686: Simplify vt82c686b_realize(), Philippe Mathieu-Daudé, 2021/02/21
- [PULL 38/43] vt82c686: Move creation of ISA devices to the ISA bridge, Philippe Mathieu-Daudé, 2021/02/21