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[PATCH v3 09/10] target/mips: Simplify 64-bit ifdef'ry of MXU code
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v3 09/10] target/mips: Simplify 64-bit ifdef'ry of MXU code |
Date: |
Mon, 22 Feb 2021 23:39:00 +0100 |
Check for 'TARGET_LONG_BITS == 32' and simplify 64-bit ifdef'ry.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.h | 2 --
target/mips/translate.c | 18 ++++++++++--------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 1801e7f819e..a807b3d2566 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -179,10 +179,8 @@ extern TCGv bcond;
void msa_translate_init(void);
/* MXU */
-#if !defined(TARGET_MIPS64)
void mxu_translate_init(void);
bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
-#endif /* !TARGET_MIPS64 */
/* decodetree generated */
bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 609798a0bee..68b5dee4bab 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25850,6 +25850,15 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
return true;
}
+#else /* !defined(TARGET_MIPS64) */
+
+bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
+{
+ return false;
+}
+
+#endif /* defined(TARGET_MIPS64) */
+
/*
* Main MXU decoding function
*/
@@ -25871,9 +25880,6 @@ static void decode_opc_mxu(DisasContext *ctx, uint32_t
insn)
decode_ase_mxu(ctx, insn);
}
-#endif /* !defined(TARGET_MIPS64) */
-
-
static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd;
@@ -27017,12 +27023,10 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
break;
}
#endif
-#if !defined(TARGET_MIPS64)
- if (ctx->insn_flags & ASE_MXU) {
+ if ((TARGET_LONG_BITS == 32) && (ctx->insn_flags & ASE_MXU)) {
decode_opc_mxu(ctx, ctx->opcode);
break;
}
-#endif
decode_opc_special2_legacy(env, ctx);
break;
case OPC_SPECIAL3:
@@ -28081,9 +28085,7 @@ void mips_tcg_init(void)
cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
"llval");
-#if !defined(TARGET_MIPS64)
mxu_translate_init();
-#endif /* !TARGET_MIPS64 */
}
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
--
2.26.2
- [PATCH v3 04/10] target/mips: Pass instruction opcode to decode_opc_mxu(), (continued)
- [PATCH v3 04/10] target/mips: Pass instruction opcode to decode_opc_mxu(), Philippe Mathieu-Daudé, 2021/02/22
- [PATCH v3 05/10] target/mips: Extract decode_ase_mxu() from decode_opc_mxu(), Philippe Mathieu-Daudé, 2021/02/22
- [PATCH v3 06/10] target/mips: Use OPC_MUL instead of OPC__MXU_MUL, Philippe Mathieu-Daudé, 2021/02/22
- [PATCH v3 07/10] target/mips: Introduce mxu_translate_init() helper, Philippe Mathieu-Daudé, 2021/02/22
- [PATCH v3 08/10] target/mips: Make mxu_translate_init() / decode_ase_mxu() proto public, Philippe Mathieu-Daudé, 2021/02/22
- [PATCH v3 09/10] target/mips: Simplify 64-bit ifdef'ry of MXU code,
Philippe Mathieu-Daudé <=
- [PATCH v3 10/10] target/mips: Extract MXU code to new mxu_translate.c file, Philippe Mathieu-Daudé, 2021/02/22