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[PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus VS field
From: |
frank . chang |
Subject: |
[PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus VS field |
Date: |
Fri, 26 Feb 2021 11:17:48 +0800 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ba4c1c7076f..73e88c2a7b1 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -414,6 +414,7 @@
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP 0x00000100
+#define SSTATUS_VS 0x00000600
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 778d5b85e92..098de1abacb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -440,7 +440,7 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+ SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD | SSTATUS_VS;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP |
MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
--
2.17.1
- [PATCH v7 00/75] support vector extension v1.0, frank . chang, 2021/02/25
- [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/02/25
- [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/02/25
- [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/02/25
- [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus VS field,
frank . chang <=
- [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/02/25
- [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/02/25
- [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/02/25
- [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/02/25
- [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/02/25
- [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/02/25
- [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/02/25
- [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/02/25
- [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/02/25
- [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2021/02/25