[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v7 38/75] target/riscv: rvv-1.0: whole register move instructions
From: |
frank . chang |
Subject: |
[PATCH v7 38/75] target/riscv: rvv-1.0: whole register move instructions |
Date: |
Fri, 26 Feb 2021 11:18:22 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvv.c.inc | 25 +++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8516a12b126..beef6ca7167 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -625,6 +625,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111
@r_vm
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
+vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
+vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
+vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
+vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 63e31299b3b..f92e5c806c8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3489,3 +3489,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
}
return false;
}
+
+/*
+ * Whole Vector Register Move Instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 17.6)
+ */
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
+static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
+{ \
+ if (require_rvv(s) && \
+ QEMU_IS_ALIGNED(a->rd, LEN) && \
+ QEMU_IS_ALIGNED(a->rs2, LEN)) { \
+ /* EEW = 8 */ \
+ tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
+ vreg_ofs(s, a->rs2), \
+ s->vlen / 8 * LEN, s->vlen / 8 * LEN); \
+ mark_vs_dirty(s); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
--
2.17.1
- [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction, (continued)
- [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/02/25
- [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/02/25
- [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/02/25
- [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/02/25
- [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/02/25
- [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/02/25
- [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/02/25
- [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/02/25
- [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/02/25
- [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/02/25
- [PATCH v7 38/75] target/riscv: rvv-1.0: whole register move instructions,
frank . chang <=
- [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/02/25
- [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/02/25
- [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/02/25
- [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/02/25
- [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/02/25
- [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/02/25
- [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/02/25
- [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/02/25
- [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/02/25
- [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/02/25