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[PATCH 09/50] target/i386: Assert !VM86 for x86_64 user-only
From: |
Richard Henderson |
Subject: |
[PATCH 09/50] target/i386: Assert !VM86 for x86_64 user-only |
Date: |
Sun, 28 Feb 2021 15:22:40 -0800 |
For i386-linux-user, we can enter vm86 mode via the vm86(2) syscall.
That syscall explicitly returns to 32-bit mode, and the syscall does
not exist for a 64-bit x86_64 executable.
Since we're adding an accessor macro, pull the value directly out of
flags otherwise.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/tcg/translate.c | 40 ++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 5f24615826..0e4f34f201 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -116,7 +116,6 @@ typedef struct DisasContext {
#endif
int addseg; /* non zero if either DS/ES/SS have a non zero base */
int f_st; /* currently unused */
- int vm86; /* vm86 mode */
int tf; /* TF cpu flag */
int jmp_opt; /* use direct block chaining for direct jumps */
int repz_opt; /* optimize jumps within repz instructions */
@@ -159,6 +158,11 @@ typedef struct DisasContext {
#define CPL(S) ((S)->cpl)
#define IOPL(S) ((S)->iopl)
#endif
+#if defined(CONFIG_USER_ONLY) && defined(TARGET_X86_64)
+#define VM86(S) false
+#else
+#define VM86(S) (((S)->flags & HF_VM_MASK) != 0)
+#endif
static void gen_eob(DisasContext *s);
static void gen_jr(DisasContext *s, TCGv dest);
@@ -631,7 +635,7 @@ static void gen_check_io(DisasContext *s, MemOp ot,
target_ulong cur_eip,
{
target_ulong next_eip;
- if (PE(s) && (CPL(s) > IOPL(s) || s->vm86)) {
+ if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
switch (ot) {
case MO_8:
@@ -1309,7 +1313,7 @@ static bool check_cpl0(DisasContext *s)
/* If vm86, check for iopl == 3; if not, raise #GP and return false. */
static bool check_vm86_iopl(DisasContext *s)
{
- if (!s->vm86 || IOPL(s) == 3) {
+ if (!VM86(s) || IOPL(s) == 3) {
return true;
}
gen_exception_gpf(s);
@@ -1319,7 +1323,7 @@ static bool check_vm86_iopl(DisasContext *s)
/* Check for iopl allowing access; if not, raise #GP and return false. */
static bool check_iopl(DisasContext *s)
{
- if (s->vm86 ? IOPL(s) == 3 : CPL(s) <= IOPL(s)) {
+ if (VM86(s) ? IOPL(s) == 3 : CPL(s) <= IOPL(s)) {
return true;
}
gen_exception_gpf(s);
@@ -2359,7 +2363,7 @@ static inline void gen_op_movl_seg_T0_vm(DisasContext *s,
X86Seg seg_reg)
call this function with seg_reg == R_CS */
static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg)
{
- if (PE(s) && !s->vm86) {
+ if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32);
/* abort translation because the addseg value may change or
@@ -4615,7 +4619,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
case 0xc4: /* 3-byte VEX */
/* VEX prefixes cannot be used except in 32-bit mode.
Otherwise the instruction is LES or LDS. */
- if (s->code32 && !s->vm86) {
+ if (s->code32 && !VM86(s)) {
static const int pp_prefix[4] = {
0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
};
@@ -5119,7 +5123,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, s->T0, s->A0);
do_lcall:
- if (PE(s) && !s->vm86) {
+ if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1,
tcg_const_i32(dflag - 1),
@@ -5146,7 +5150,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
gen_add_A0_im(s, 1 << ot);
gen_op_ld_v(s, MO_16, s->T0, s->A0);
do_ljmp:
- if (PE(s) && !s->vm86) {
+ if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1,
tcg_const_tl(s->pc - s->cs_base));
@@ -6579,7 +6583,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
case 0xca: /* lret im */
val = x86_ldsw_code(env, s);
do_lret:
- if (PE(s) && !s->vm86) {
+ if (PE(s) && !VM86(s)) {
gen_update_cc_op(s);
gen_jmp_im(s, pc_start - s->cs_base);
gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1),
@@ -6605,7 +6609,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
goto do_lret;
case 0xcf: /* iret */
gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
- if (!PE(s) || s->vm86) {
+ if (!PE(s) || VM86(s)) {
/* real mode or vm86 mode */
if (!check_vm86_iopl(s)) {
break;
@@ -7309,7 +7313,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
op = (modrm >> 3) & 7;
switch(op) {
case 0: /* sldt */
- if (!PE(s) || s->vm86)
+ if (!PE(s) || VM86(s))
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
tcg_gen_ld32u_tl(s->T0, cpu_env,
@@ -7318,7 +7322,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 2: /* lldt */
- if (!PE(s) || s->vm86)
+ if (!PE(s) || VM86(s))
goto illegal_op;
if (check_cpl0(s)) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
@@ -7328,7 +7332,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
}
break;
case 1: /* str */
- if (!PE(s) || s->vm86)
+ if (!PE(s) || VM86(s))
goto illegal_op;
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
tcg_gen_ld32u_tl(s->T0, cpu_env,
@@ -7337,7 +7341,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
break;
case 3: /* ltr */
- if (!PE(s) || s->vm86)
+ if (!PE(s) || VM86(s))
goto illegal_op;
if (check_cpl0(s)) {
gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
@@ -7348,7 +7352,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
break;
case 4: /* verr */
case 5: /* verw */
- if (!PE(s) || s->vm86)
+ if (!PE(s) || VM86(s))
goto illegal_op;
gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0);
gen_update_cc_op(s);
@@ -7719,7 +7723,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
TCGLabel *label1;
TCGv t0, t1, t2, a0;
- if (!PE(s) || s->vm86)
+ if (!PE(s) || VM86(s))
goto illegal_op;
t0 = tcg_temp_local_new();
t1 = tcg_temp_local_new();
@@ -7767,7 +7771,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
{
TCGLabel *label1;
TCGv t0;
- if (!PE(s) || s->vm86)
+ if (!PE(s) || VM86(s))
goto illegal_op;
ot = dflag != MO_16 ? MO_32 : MO_16;
modrm = x86_ldub_code(env, s);
@@ -8483,12 +8487,12 @@ static void i386_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cpu)
g_assert(PE(dc) == ((flags & HF_PE_MASK) != 0));
g_assert(CPL(dc) == cpl);
g_assert(IOPL(dc) == iopl);
+ g_assert(VM86(dc) == ((flags & HF_VM_MASK) != 0));
dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
dc->f_st = 0;
- dc->vm86 = (flags >> VM_SHIFT) & 1;
dc->tf = (flags >> TF_SHIFT) & 1;
dc->cc_op = CC_OP_DYNAMIC;
dc->cc_op_dirty = false;
--
2.25.1
- [PATCH 00/50] i386 cleanup part 3, Richard Henderson, 2021/02/28
- [PATCH 01/50] target/i386: Split out gen_exception_gpf, Richard Henderson, 2021/02/28
- [PATCH 03/50] target/i386: Unify code paths for IRET, Richard Henderson, 2021/02/28
- [PATCH 02/50] target/i386: Split out check_cpl0, Richard Henderson, 2021/02/28
- [PATCH 05/50] target/i386: Split out check_iopl, Richard Henderson, 2021/02/28
- [PATCH 07/50] target/i386: Assert CPL is 3 for user-only, Richard Henderson, 2021/02/28
- [PATCH 04/50] target/i386: Split out check_vm86_iopl, Richard Henderson, 2021/02/28
- [PATCH 11/50] target/i386: Assert SS32 for x86_64 user-only, Richard Henderson, 2021/02/28
- [PATCH 09/50] target/i386: Assert !VM86 for x86_64 user-only,
Richard Henderson <=
- [PATCH 08/50] target/i386: Assert IOPL is 0 for user-only, Richard Henderson, 2021/02/28
- [PATCH 06/50] target/i386: Assert PE is set for user-only, Richard Henderson, 2021/02/28
- [PATCH 13/50] target/i386: Assert LMA for x86_64 user-only, Richard Henderson, 2021/02/28
- [PATCH 12/50] target/i386: Assert CODE64 for x86_64 user-only, Richard Henderson, 2021/02/28
- [PATCH 18/50] target/i386: Move rex_w into DisasContext, Richard Henderson, 2021/02/28
- [PATCH 10/50] target/i386: Assert CODE32 for x86_64 user-only, Richard Henderson, 2021/02/28
- [PATCH 15/50] target/i386: Introduce REX_PREFIX, Richard Henderson, 2021/02/28
- [PATCH 16/50] target/i386: Tidy REX_B, REX_X definition, Richard Henderson, 2021/02/28
- [PATCH 19/50] target/i386: Remove DisasContext.f_st as unused, Richard Henderson, 2021/02/28
- [PATCH 21/50] target/i386: Reduce DisasContext.override to int8_t, Richard Henderson, 2021/02/28